arch/riscv: Fix the page table setup code
authorJonathan Neuschäfer <j.neuschaefer@gmx.net>
Tue, 9 Aug 2016 00:07:12 +0000 (02:07 +0200)
committerRonald G. Minnich <rminnich@gmail.com>
Thu, 11 Aug 2016 19:12:54 +0000 (21:12 +0200)
commit1394bba6bb9e8dc48afb4fe6107d8e64ee5e6855
treecce5ebb12c6cc6760b90ec993f50a2be0d797d4f
parentc42b5917af50a1a0b6a64330e9cdd953c46102b7
arch/riscv: Fix the page table setup code

In particular:

- Fix the condition of the loop that fills the mid-level page table
- Adhere to the format of sptbr

Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16120
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
src/arch/riscv/virtual_memory.c