arch/riscv: Fix the page table setup code
authorJonathan Neuschäfer <j.neuschaefer@gmx.net>
Tue, 9 Aug 2016 00:07:12 +0000 (02:07 +0200)
committerRonald G. Minnich <rminnich@gmail.com>
Thu, 11 Aug 2016 19:12:54 +0000 (21:12 +0200)
In particular:

- Fix the condition of the loop that fills the mid-level page table
- Adhere to the format of sptbr

Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16120
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
src/arch/riscv/virtual_memory.c

index 385a5fd..bbbba7a 100644 (file)
@@ -74,7 +74,9 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable
                root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i);
 
        // fill the middle page table
-       for (uintptr_t vaddr = virtMemStart, paddr = physMemStart; paddr < memorySize; vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) {
+       for (uintptr_t vaddr = virtMemStart, paddr = physMemStart;
+                       paddr < physMemStart + memorySize;
+                       vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) {
                int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT;
                size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1);
                l2_idx += ((vaddr - virtMemStart) >> l2_shift);
@@ -95,7 +97,8 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable
 
        mb();
        root_page_table = root_pt;
-       write_csr(sptbr, root_pt);
+       uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT;
+       write_csr(sptbr, ptbr);
 }
 
 void initVirtualMemory(void) {