soc/apollolake: enable access to RTC NVRAM
authorRavi Sarawadi <ravishankar.sarawadi@intel.com>
Wed, 10 Aug 2016 18:33:56 +0000 (11:33 -0700)
committerFurquan Shaikh <furquan@google.com>
Thu, 11 Aug 2016 20:43:53 +0000 (22:43 +0200)
FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region

BUG=chrome-os-partner:55944
TEST=Check 'crossystem dev_boot_usb=1'

Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
src/soc/intel/apollolake/chip.c

index 345d7c4..1b109d0 100644 (file)
@@ -397,6 +397,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
        /* Disable setting of EISS bit in FSP. */
        silconfig->SpiEiss = 0;
+
+       /* Disable FSP from locking access to the RTC NVRAM */
+       silconfig->RtcLock = 0;
 }
 
 struct chip_operations soc_intel_apollolake_ops = {