cros-ec.git
4 years agokevin / gru: Remove task profiling to improve SHI interrupt latency master
Shawn Nematbakhsh [Thu, 28 Jul 2016 22:09:45 +0000 (15:09 -0700)]
kevin / gru: Remove task profiling to improve SHI interrupt latency

BUG=chrome-os-partner:55710
BRANCH=None
TEST=Manual on gru with subsequent commit. Verify `flashrom -p ec -r
file.bin` passes 100x with no errors or warnings.

Change-Id: Id208ebc5d402518012f9adc10f86d8b4de5a35ce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364235
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agogru: Align images sizes to flash block erase size
Shawn Nematbakhsh [Mon, 1 Aug 2016 22:09:22 +0000 (15:09 -0700)]
gru: Align images sizes to flash block erase size

Image sizes must be aligned to block erase size to ensure that the host
can erase the entire image and nothing but the image.

BUG=chrome-os-partner:55828
BRANCH=None
TEST=Manual on kevin, rebuild FW with new EC, rebuild + flash EC once
again, verify that SW sync completes and unit boots to OS.

Change-Id: If6110f39869d6421038a3fe7afdc7d918323249e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365142
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agotpm: make TPM_FW_VER register return both build and version strings
Vadim Bendebury [Sun, 31 Jul 2016 00:40:45 +0000 (17:40 -0700)]
tpm: make TPM_FW_VER register return both build and version strings

Both build string (which includes status of all firmware components of
the running image) and the firmware version string (which show
versions of various objects in the flash) are important to the user.

Let's include both of these strings into the TPM_FW_VER register
output. Buffer storing the string needs to be increased accordingly.

BRANCH=none
BUG=chrome-os-partner:55558
TEST=verified the contents of the AP firmware console log:

localhost ~ # grep cr50 /sys/firmware/log
Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A: ...
cr50_v1.1.5003-af11829+ private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735...

Change-Id: I67df3e810bd07053d0b7d8b6fac350253ca06bb0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364830
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agog: disable sps as a wake source in deep sleep
Mary Ruthven [Thu, 28 Jul 2016 01:43:51 +0000 (18:43 -0700)]
g: disable sps as a wake source in deep sleep

Cr50 cant retain the TPM state in deep sleep so it wont be enabled until
it knows that the AP is off. If the AP is off it wont be asserting
SPS_CS_L, but it may be low because the AP isn't pulling it up.
This change disables it as a wake source in deep sleep.

BUG=chrome-os-partner:54796
BRANCH=none
TEST=run 'idle d'. Make sure cr50 goes into deep sleep and only resumes
due to a rdd event or when sys_rst_l is asserted.

Change-Id: Idf3ded6b439b71a27ac7eb4682a65dcdd6342cb9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364864
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoreef: Enable thermal sensors
David Hendricks [Fri, 15 Jul 2016 01:10:58 +0000 (18:10 -0700)]
reef: Enable thermal sensors

BUG=chrome-os-partner:54818
BRANCH=none
TEST=field
CQ-DEPEND=CL:363008

Change-Id: I236e7e39f4d60e9bd758c387c93ac57e64868bf8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360722
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agothermistor: Add generic linear interpolation algorithm
David Hendricks [Sat, 14 May 2016 03:24:56 +0000 (20:24 -0700)]
thermistor: Add generic linear interpolation algorithm

The existing algorithm makes several assumptions for a particular
thermistor circuit. This patch introduces a more generic version
that can be used for multiple thermistors on a single board.

The idea is to approximate a curve produced by solving for voltage
measued by an ADC using the Steinhart-Hart equation. For a straight
line one only needs two data points. For a steady curve data
points can be distributed evenly. For the most part, though, data
points should be provided after a significant change in slope.

More data points give more accuracy at the expense of memory, and
we mostly only care about accuracy in the range between "warm"
and "too hot" so only a few data points should be used.

BUG=chrome-os-partner:54818
BRANCH=none
TEST=added unit test, needs real testing

Change-Id: I046e61dbfd1e8c26c2a533777f222f5413938556
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344781
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agog: increase usb console TX buffer size to 4K
Vadim Bendebury [Sun, 31 Jul 2016 17:15:31 +0000 (10:15 -0700)]
g: increase usb console TX buffer size to 4K

Increasing the USB console TX buffer size allows to see pretty much
all early startup messages generated before USB console is
initialized.

There is still plenty of room left in SRAM, 23K on cr50, much more on
all other g based boards.

BRANCH=none
BUG=none
TEST=observed better USB console output on cr50 restarts.

Change-Id: I82f37ee7f3aecd8b7e95f3d421789c11375b2fd4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364811
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Nadim Taha <ntaha@chromium.org>
4 years agogru: support lid accelerometer
Brian Norris [Sat, 30 Jul 2016 01:35:32 +0000 (18:35 -0700)]
gru: support lid accelerometer

BRANCH=none
BUG=chrome-os-partner:55758
TEST=gru tablet mode

Change-Id: I4396f39da74f8ef409d4d335cdef92d2697f7421
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364842
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agotpm: allow TPM_FW_VER register to return arbitrary number of bytes
Vadim Bendebury [Sun, 31 Jul 2016 00:45:31 +0000 (17:45 -0700)]
tpm: allow TPM_FW_VER register to return arbitrary number of bytes

As the version string grows longer, reading it in 4 byte chunks
becomes more and more expensive, the overhead of setting up a separate
SPI transaction per very chunk is just too much.

There is no reason not to allow the host to read as many bytes at a
time as it requires (limiting it by the maximum version string buffer
size of course).

BRANCH=none
BUG=chrome-os-partner:55558
TEST=verified that the version string is still read properly by the
     TPM driver on Kevin

Change-Id: Ib76cd151e8dc32374f87135af36266b4ec725a56
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364831
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agog: use single buffer for version reporting
Vadim Bendebury [Sat, 30 Jul 2016 02:09:30 +0000 (19:09 -0700)]
g: use single buffer for version reporting

The only place where two separate buffers for the RO version strings
is required is the tpm_registers.c:set_version_string() function.

In preparation of reporting the build string along with the version
string, let's rearrange the function not to require separate buffers
for the RO versions.

BRANCH=none
BUG=chrome-os-partner:55558

TEST=verified that version reported by the TPM driver on Kevin is
     still correct:

  localhost ~ # grep cr50 /sys/firmware/log
  Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:*...

Change-Id: I8924ac48bd838851670f0d659e95aa92a8524665
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364587
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agosystem: split long build lines
Vadim Bendebury [Fri, 29 Jul 2016 03:40:55 +0000 (20:40 -0700)]
system: split long build lines

Some boards now provide very long build version strings including
version strings of multiple subcomponents.

Let the version command split those long lines printing each
subcomponent's version string in a separate line.

BRANCH=none
BUG=chrome-os-partner:55373
TEST=verified on cr50:
  > vers
  Chip:    g cr50 B2
  Board:   0
  RO_A:    0.0.1/84e2dde7
  RO_B:  * 0.0.2/13eda43f
  RW_A:  * cr50_v1.1.4980-2b9f3e1
  RW_B:    cr50_v1.1.4979-8cec36d+
  Build:   cr50_v1.1.4980-2b9f3e1
           private-cr51:v0.0.66-bd9a0fe
           tpm2:v0.0.259-2b12863
           cryptoc:v0.0.4-5319e83
           2016-07-28 20:40:55 vbendeb@kvasha

Change-Id: Ie14af3aa9febd5a3b02b273a7ab6302e74777e43
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364491

4 years agoseparate dptf logic from existing thermal logic.
Ravi Chandra Sadineni [Tue, 26 Jul 2016 01:06:29 +0000 (18:06 -0700)]
separate dptf logic from existing thermal logic.

Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
BRANCH=none
BUG=chromium:631848
TEST=make buildall -j

Change-Id: I718a29b067d37af477306f9bebfcb8e71d84d4ee
Reviewed-on: https://chromium-review.googlesource.com/363008
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
4 years agoUse CONFIG_DPTF flag instead of THROTTLE_AP.
Ravi Chandra Sadineni [Wed, 27 Jul 2016 01:04:09 +0000 (18:04 -0700)]
Use CONFIG_DPTF flag instead of THROTTLE_AP.

Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
BRANCH=none
BUG=chromium:631848
TEST=make buildall -j
CQ-DEPEND=CL:363008

Change-Id: I3c35f5ab2e3a1537ac6e8c750171d5c2b3a6570f
Reviewed-on: https://chromium-review.googlesource.com/363583
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
4 years agoutil: do not generate unrelated version information
Vadim Bendebury [Fri, 29 Jul 2016 23:55:55 +0000 (16:55 -0700)]
util: do not generate unrelated version information

The recent addition of the multicomponent version string for cr50,
requires further tweaking of the version generating script. In
particular, the CROS_EC_VERSION32 variable used by the "verson" cli
command is not supposed to include any information about subcomponents
of the image, it should reflect the EC version only.

Separating everything after the first space accomplishes that.

BRANCH=none
BUG=chrome-os-partner:55373
TEST=verified that RO_x and RW_x versions are printed properly:
  > vers
  Chip:    g cr50 B2
  Board:   0
  RO_A:    0.0.1/84e2dde7
  RO_B:  * 0.0.3/8fe06b9e
  RW_A:    cr50_v1.1.4992-7c9f891+ private
  RW_B:  * cr50_v1.1.4989-52b3cc6+
  ...

Change-Id: I192eb29816dfa963b08aa97f749b978b1367d6b7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364490
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoRevert "charger: bd99955: Adjust VSYS based on fast vs precharge state"
Shawn Nematbakhsh [Sat, 30 Jul 2016 00:09:35 +0000 (17:09 -0700)]
Revert "charger: bd99955: Adjust VSYS based on fast vs precharge state"

This reverts commit 7369f0a68912dbd749271b79606c569071db0a13. Keep VSYS
constant throughout precharge / fastcharge.

BUG=chrome-os-partner:55524
BRANCH=None
TEST=Build only.

Change-Id: I35cda81b42833af2c860f35dd492ecb4f1e49025
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364625
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agoHACK tpm: reset fallback counter when ready
Vadim Bendebury [Fri, 29 Jul 2016 00:17:19 +0000 (17:17 -0700)]
HACK tpm: reset fallback counter when ready

As a temp measure until a proper solution is implemented, reset the
restart counter when the PCR_Read command is issued by the host.

This is a good indication that Chrome OS is through the boot process,
as PCR value is used to determine the boot mode.

BRANCH=none
BUG=chrome-os-partner:55667
TEST=installed the new image on a Kevin cr50 and rebooted it in normal
     and recovery modes, observed on the cr50 console the message like
  > system_process_retry_counter:retry counter 1

Change-Id: Ib55e161d5edbf8f6e2d387fd756b94aa53c20ed8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364311
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoreef led: add battery led support
li feng [Wed, 27 Jul 2016 23:24:07 +0000 (16:24 -0700)]
reef led: add battery led support

BUG=chrome-os-partner:55492
BRANCH=none
TEST=on Reef proto, verified led behavior on battery charing,
discharging cases

Change-Id: Ibc134b741e5c433697b752f73bd3e29ba5910124
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/364025
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agotcpm: anx74xx: Fix cable orientation detection
Divya Sasidharan [Fri, 29 Jul 2016 16:57:13 +0000 (09:57 -0700)]
tcpm: anx74xx: Fix cable orientation detection

Aux switch settings set the polarity and this happens once on every
cable connect. But when the cable is kept connected if the mux is
set to 0 this is also reset and remains 0 for any next valid mux state.

BRANCH=ToT
BUG=chrome-os-partner:55757
TEST=manual:on reef, plug HDMI type-C dongle and check if DUT screen
    is displayed on HDMI display for both the orientation.

Change-Id: Ie1320d11d1927acb292dbaf4c932b48cdfd7768e
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/364693
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agocts: Add timer test
Daisuke Nojiri [Mon, 18 Jul 2016 22:12:32 +0000 (15:12 -0700)]
cts: Add timer test

The timer test checks the accuracy of the internal timer. After sync,
DUT and TH start counting down one second. After one second, DUT raises
GPIO level.  TH determines whether the test passes or not based on how
much more or less time elapsed than one second, assuming its clock is
calibrated.

This test takes advantage of TH running on a bare chip. If the host
were measuring (instead of TH), the timing would be affected by many
software and hardware layers (e.g. UART drivers on DUT and host,
python interpreter, etc.).

BUG=chromium:624520
BRANCH=none
TEST=cts.py --module timer && cts.py --module gpio && make buildall

Change-Id: I535e7772b4d93f1f5d248506f7ea167429a50174
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361384

4 years agonpcx: shi: Improve host command handling reliability
Shawn Nematbakhsh [Thu, 28 Jul 2016 21:39:44 +0000 (14:39 -0700)]
npcx: shi: Improve host command handling reliability

- Pass-thru to IBF handler code in case both IBHF and IBF interrupts are
  pending, in order to properly keep track our Tx byte count.
- Don't disable the SHI IRQ in our host command handler callback since
  system-wide interrupts are already disabled.

BUG=chrome-os-partner:55711,chrome-os-partner:55721
BRANCH=None
TEST=Manual on gru with subsequent commit. Verify `flashrom -p ec -r
file.bin` passes 100x with no errors or warnings.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6225ffde1fe0127c7484933fe4a151d22f42415c
Reviewed-on: https://chromium-review.googlesource.com/364234
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
4 years agog: lock the active bootloader, just in case
Bill Richardson [Thu, 28 Jul 2016 22:53:37 +0000 (15:53 -0700)]
g: lock the active bootloader, just in case

Whether the bootrom locks the bootloader or not is deteremined by
fuses and/or flags in the bootloader's signed header. This CL
locks the active bootloader, just case those aren't configured to
do so.

BUG=chrome-os-partner:55261
BRANCH=none
TEST=manual

On an unlocked bootloader, I see this after booting:

  > rw 0x40090100
  read 0x40090100 = 0x00000001

With this CL applied, I see this instead:

  > rw 0x40090100
  read 0x40090100 = 0x00000000

Change-Id: I2e1396b7d7e71c8633d97d3cb573e9468eeb51e7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364280
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoreef: Update pins for EVT
David Hendricks [Sat, 16 Jul 2016 00:27:54 +0000 (17:27 -0700)]
reef: Update pins for EVT

Updates for EVT:
- TCPC0 interrupt polarity is now low, define GPIO_INT and set ANX74xx
  internal polarity control based on IS_PROTO.
- Swapped pin assignments for USB_C1_PD_INT_ODL and EN_USB_C1_5V_OUT.
- Rename USB_PD_RST_ODL to USB_C0_PD_RST_L and make it push-pull.
- Add USB_C1_PD_RST_ODL

BUG=chrome-os-partner:54958,chrome-os-partner:54952,chrome-os-partner:55165
BRANCH=none
TEST=needs testing

Change-Id: I075934cced532d656f942841c30e3640a6f42568
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358944
Reviewed-by: Duncan Laurie <dlaurie@google.com>
4 years agoreef: Check if interrupt is active in tcpc_alert_event
David Hendricks [Sat, 16 Jul 2016 01:28:34 +0000 (18:28 -0700)]
reef: Check if interrupt is active in tcpc_alert_event

This ensures that we're only checking the reset signal for the
corresponding interrupt. Otherwise we can hit a race condition
when both TCPC chips are taken out of reset.

(This is also how it's done on Amenia)

BUG=none
BRANCH=none
TEST=needs testing

Change-Id: I47513b3b47e947c8b4644f4d837ddc3fb1ee7a30
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361061
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agoreef: Initialize TCPC chips in their own function
David Hendricks [Sat, 16 Jul 2016 02:27:16 +0000 (19:27 -0700)]
reef: Initialize TCPC chips in their own function

This makes board_set_tcpc_power_mode() a noop since that's controlled
by anx74xx code and we have another TCPC chip onboard. Instead, we'll
reset the TCPC chips in a hook that will run after board and I2C init.

This is more like what Amenia code does.

BUG=chrome-os-partner:54952
BRANCH=none
TEST=needs testing.

Change-Id: Id3af4af1014432235b699a9568ee19df63601b2c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361060
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agonpcx: Consecutively sample IBUFSTAT until reading the same value twice
CHLin [Mon, 25 Jul 2016 06:35:01 +0000 (14:35 +0800)]
npcx: Consecutively sample IBUFSTAT until reading the same value twice

It has rare chance for FW to get a unexpected value when reading
IBUFSTAT. This is because the clock source of SHI and CPU are
asynchronous. The reading value is invalid if IBUFSTAT is during
transition state. Use two consecutive equal reading can make sure
the value is valid.

BUG=chrome-os-partner:34346
TEST=run "while true; do ectool version; done" on gru, verify each
failure happens about 50000 host commands
BRANCH=none

Change-Id: Ie246561d201dd87d89cb2424c23d016dcdcd47c9
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/362734
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
4 years agoprintf: Add sign ('+') flag
Daisuke Nojiri [Wed, 27 Jul 2016 21:06:17 +0000 (14:06 -0700)]
printf: Add sign ('+') flag

'+' flag can be used with signed integer type (%d) and causes positive
integers to be prefixed with '+' (e.g. +1745). This emphasizes output
values as a signed value. It can be mixed with left-justification flag
'-': %-+8d. It's ignored when used with unsigned integer or non-integer
types: %u, %x, %p, %s, %c, etc.

BUG=none
BRANCH=none
TEST=make buildall &&
int32_t d = 1745;
CPRINTS("'%-+8d'", -d);     /* '-1745    ' */
CPRINTS("'%-+8d'", d);      /* '+1745    ' */
CPRINTS("'%d'", d);         /* '1745' */
CPRINTS("'%+08d'", -d);     /* '000-1745' */
CPRINTS("'%+08d'", d);      /* '000+1745' */
CPRINTS("'%+d'", -d);       /* '-1745' */
CPRINTS("'%+d'", d);        /* '+1745' */
CPRINTS("'%+s'", "foo");    /* 'foo' */
CPRINTS("'%-+8s'", "foo");  /* 'foo     ' */
CPRINTS("'%+08x'", d);      /* '000006d1' */
CPRINTS("'%+u'", d);        /* '1745' */

Change-Id: I8dcd34b0cf03dbefc500b9c98fea235d85bde8d3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363924

4 years agostm32l4: Enable extended interrupts (EXTI)
Daisuke Nojiri [Mon, 25 Jul 2016 23:11:06 +0000 (16:11 -0700)]
stm32l4: Enable extended interrupts (EXTI)

BUG=none
BRANCH=none
TEST=Validated by CTS timer test (up-coming)

Change-Id: I9c23e7dbfab779dc4e847fa5c9b93bee484e55e2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363007
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Chris Chen <twothreecc@google.com>
4 years agopd: tcpci: Fix tcpci_tcpm_set_vconn() to set bit0 (VCONN) only.
Koro Chen [Fri, 15 Jul 2016 03:52:30 +0000 (11:52 +0800)]
pd: tcpci: Fix tcpci_tcpm_set_vconn() to set bit0 (VCONN) only.

Previously, tcpci_tcpm_set_vconn() would set bit0 and clear all others
of POWER_CTRL. With this patch, only bit0 is updated.

BRANCH=oak
BUG=chrome-os-partner:55221
TEST=plug/unplug apple dongle, check TCPCI 0x1c bit4 should be always 1

Change-Id: I83f113c13bdaad8ce6ece56241296a8f097e1f0a
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360771
Reviewed-by: Todd Broch <tbroch@chromium.org>
4 years agoutil: collect cr50 versions from multiple git trees
Vadim Bendebury [Thu, 28 Jul 2016 05:45:28 +0000 (22:45 -0700)]
util: collect cr50 versions from multiple git trees

The cr50 code comes from four different repositories. This patch
introduces an array of the repositories where version information is
supposed to come from.

For all boards but cr50 this array includes just the local repository,
for cr50 the array is extended with the three other components.

This patch also allows to change the 'tree dirty' marker appended to
the sha1s of the 'dirty' trees, having a shorter marker helps to keep
multicomponent version strings shorter.

All external component's version information in the generated combined
version string is prepended by the component's root directory name.

BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script for two EC boards, kevin and cr50, verified the
     output:

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
 * in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
 * in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

then introduced some local changes in the ec and tpm2 directories and
ran the script again. Note the '+' used as the 'dirty' marker in the
cr50 string:

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
 * in common/version.c. */
/* Repo is dirty, using time of last compilation */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
 * in common/version.c. */
/* Repo is dirty, using time of last compilation */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Change-Id: I4b4ec23ce003970c09442e8d8aeed2306d4e5dd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363917
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocr50: fix usb spi to disable resets while doing updates
Mary Ruthven [Thu, 28 Jul 2016 00:45:04 +0000 (17:45 -0700)]
cr50: fix usb spi to disable resets while doing updates

We need to ignore sys_rst_l right now when we use the usb spi endpoint
to update the AP or EC. We hold the EC and AP in reset and this causes
sys_rst_l to be asserted at the start of updating the AP and when the EC
comes out of reset.

Using the USB SPI endpoint may require doing a bunch of transactions
back to back. Cr50 should not reset itself between each one.

This change postpones the reset until we're done using the usb spi
endpoint. Once sys_rst_l just resets the TPM we can remove all of this.

BUG=chrome-os-partner:52366
BUG=chrome-os-partner:54982
BRANCH=none
TEST=manual
verify 'util/flash_ec --board=kevin --raiden' updates the EC

'sudo flashrom -p raiden_debug_spi:target=AP -w $IMG' updates
the AP

The AP and cr50 reset after usb_spi is disabled.

Change-Id: I68a76012bc7bf6d3abd073a70f0b90e440d72c49
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364051
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoutil: refactor getversion.sh
Vadim Bendebury [Thu, 28 Jul 2016 03:22:26 +0000 (20:22 -0700)]
util: refactor getversion.sh

It is necessary to collect information about more then one git
repositories status for the cr50 board. To facilitate this, separate
the code retrieving build version information into a function,
get_tree_version().

The function returns a two element string, the version information and
the 'dirty' marker in case the tree has any uncommitted changes. The
0x01 character is used to join the elements of the string, which makes
it easier to split the string when processing it.

BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script before and after changes, observed that generated
      output is identical.

Change-Id: I2c211cbda8c3cab3c8c21b4430e4b3102691e74a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362849
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agog: add wake pin info to pinmux command
Mary Ruthven [Tue, 26 Jul 2016 23:35:11 +0000 (16:35 -0700)]
g: add wake pin info to pinmux command

It is useful to be able to see which pins are set as wake pins and what
type they are. This change adds prints to show_pinmux to describe the
wake pins.

BUG=none
BRANCH=none
TEST='pinmux' should show DIOA12 as a wake_low source.

Change-Id: I2a0ccdbf9b07abb627c3d52c7dd28433a2beff3c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363494
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agokevin: invert accelerometer matrix
Brian Norris [Thu, 28 Jul 2016 17:53:59 +0000 (10:53 -0700)]
kevin: invert accelerometer matrix

We have the lid and base sensors correct in relation to each other.
e.g., when at 90 degree lid angle, this reports correctly:

    # ectool motionsense lid_angle
    Lid angle: 90

But it appears that our axes are opposite from (e.g.) what Chrome
expects. With the lid angle at 180 degrees flat on a desk, I see:

    # ectool motionsense
    Motion sensing inactive
    Sensor 0: -571 1018 -16302
    Sensor 1: 0 0 0
    Sensor 2: 896 -3424 -16208

but the Z-axis should be positive. After this patch, I see:

    # ectool motionsense
    Motion sensing inactive
    Sensor 0: 580 -1000 16289
    Sensor 1: 0 0 0
    Sensor 2: -832 16368 1008

Which looks more accurate, and actually gets Chrome to rotate properly.

All tested on kevin rev3.

BRANCH=none
BUG=chrome-os-partner:55717
TEST=`ectool motionsense`, `ectool motionsense lid_angle`; also test
     rotation in Chrome

Change-Id: Ie1bffe27989c893d6037e251499f235ef10d4578
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364161
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agoCr50: Don't build native tests for this target
Bill Richardson [Wed, 27 Jul 2016 21:11:22 +0000 (14:11 -0700)]
Cr50: Don't build native tests for this target

The ancient native tests can't deal with board-specific
configurations, don't build them. We run generic changes with
host tests and board-specific cases by running on real hardware.

BUG=chrome-os-partner:55705
BRANCH=none
TEST=make BOARD=cr50 tests; make buildall; test on Cr50 hardware

Change-Id: I5eb7229ca9df16293d6f0f84b474d4c992277baf
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363942
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agocr50: fix wake pin handling when resuming from sleep
Mary Ruthven [Mon, 25 Jul 2016 23:14:15 +0000 (16:14 -0700)]
cr50: fix wake pin handling when resuming from sleep

Cr50 was not waking up long enough after SPS_CS_L was asserted for the
spi slave transactions to start and disable sleep. It also was not
handling SYS_RST_L properly when it was asleep.

This change sets SPS_CS_L to be an edge triggered wake up source instead
of level triggered, because cr50 should just wake up on the edge and
disable sleep until the spi transaction is done.

It also adds sys_rst_l as a wakeup source. The sys_rst_asserted
interrupt cannot be triggered while cr50 is asleep, so the
pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at
resume. This change relies on the EC extending the delay in
chipset_reset to be long enough for SYS_RST_L to still be asserted when
cr50 resumes.

BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
make sure suzyq is disconnected.

verify ap boots up to the kernel after running
'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec
console.

Check that cr50 goes to sleep when the AP is not trying to use
the TPM.

When cr50 is asleep pwrbtn + refresh still resets the system.

Disable SYS_RST_L_IN as a wake source and verify the system
verification fails and requests a recovery image.

Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363606
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoReenable "Cr50: Set the default idle action to Sleep"
Mary Ruthven [Wed, 27 Jul 2016 00:20:46 +0000 (00:20 +0000)]
Reenable "Cr50: Set the default idle action to Sleep"

Cr50 sleep has been fixed so we can now set the default idle action to
sleep.

This reverts commit 734d834becd3f8e08cdc094882aed447c6275b9f to add back
commit 9a644c429af9f299445962892666685233cb0a1b.

BUG=chrome-os-partner:54331

Change-Id: I62edffe0823f6d49a50d8e3fbde3d16f075585c8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363582
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agokevin: increase the delay in chipset_reset
Mary Ruthven [Thu, 28 Jul 2016 17:47:06 +0000 (10:47 -0700)]
kevin: increase the delay in chipset_reset

Cr50 has sys_rst_l as a wake source, but it can't tell which pin woke it
on resume. To know the source it has to check the value of the pin on
resume. This change makes the delay long enough for Cr50 to resume and
check that sys_rst_is asserted.

BUG=chrome-os-partner:55674
BUG=b:30308276
BRANCH=none
TEST=enable sleep on cr50 and verify apreset still reset it

Change-Id: I8e088c5f13a4222142161d8b79550dfc6eb529d6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364170
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agoCR50: re-enable rsa 1024-bit keygen test
nagendra modadugu [Thu, 28 Jul 2016 19:49:13 +0000 (12:49 -0700)]
CR50: re-enable rsa 1024-bit keygen test

Re-enable the RSA 1024-bit keygen test, which
was fixed by change 76ab8e6f448a3fa3f216b1c54e8a0ca4ff282a08.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:53893
TEST=test/tpm_test/tpmtest.py passes

Change-Id: Id46bcf4ce4468928bd5256a5aadbf5b62419a6e1
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/364240
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agokevin: reef: enable CCD provided by an external chip
Vincent Palatin [Tue, 26 Jul 2016 09:17:08 +0000 (11:17 +0200)]
kevin: reef: enable CCD provided by an external chip

The case close debug (CCD) feature is provided by the external security
chip. We add CONFIG_CASE_CLOSED_DEBUG_EXTERNAL to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, plug a SuzyQ (with Rd/Rd) either in S5 or
transition the device to S5 afterwards and see the debug USB endpoint
works.

Change-Id: Icef4209470463be77d43f4a46e32769ebf58f558
Reviewed-on: https://chromium-review.googlesource.com/363401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agopd: support CCD provided by an external chip
Vincent Palatin [Tue, 26 Jul 2016 09:07:52 +0000 (11:07 +0200)]
pd: support CCD provided by an external chip

When the case close debug (CCD) feature is provided by an external chip
(e.g security chip or TCPC), we still need to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).
Add a CONFIG_CASE_CLOSED_DEBUG_EXTERNAL configuration parameter for this
case.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, enable CONFIG_CASE_CLOSED_DEBUG_EXTERNAL,
plug a SuzyQ (with Rd/Rd) and verify that the device in debug mode
when transitioning to S5.

Change-Id: Ie04a000a7b0eb670e3808f7bca1180298dfcd9db
Reviewed-on: https://chromium-review.googlesource.com/363400
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agokevin: battery: Revive batteries in soft-disconnect state
Shawn Nematbakhsh [Mon, 25 Jul 2016 23:25:52 +0000 (16:25 -0700)]
kevin: battery: Revive batteries in soft-disconnect state

ESC+F3+Power+AC removal puts the battery into a soft-disconnect state
where is stops supplying current. Revive batteries in this state by
supplying a precharge current.

BUG=chrome-os-partner:55617
BRANCH=None
TEST=Manual on kevin. Put battery into soft-disconnect state. Attach
charger and verify EC doesn't lose power and battery again supplies
current.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8dfcfa90c723d627636d9bebca48429b9f1106f7
Reviewed-on: https://chromium-review.googlesource.com/363004
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agork3399: Start 'force shutdown' timer on initial power press
Shawn Nematbakhsh [Tue, 26 Jul 2016 20:11:39 +0000 (13:11 -0700)]
rk3399: Start 'force shutdown' timer on initial power press

On a power press that will bring the system to S0, start our 8 sec
timeout in case the power button is never released.

BUG=chrome-os-partner:55666
BRANCH=None
TEST=Press and hold power button on kevin to bring device to S0, verify
device boots in normal mode and powers down ~8 seconds after initial
press.

Change-Id: I1cbb52974bcc09d23a130df13815cee07968467a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363592
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agocts: Added parsing for cts suites
Chris Chen [Tue, 12 Jul 2016 19:36:55 +0000 (12:36 -0700)]
cts: Added parsing for cts suites

Added test recording when calling reset from command
line. These results are printed on the screen and
saved in /tmp/results/<board>/<module>.txt

BRANCH=None
BUG=None
TEST=Manual
- Connect, build and flash boards
- Navigate to ec/cts
- ./cts.py --run
- Find test results /tmp/results/<board>/<module>.txt
- Tests names should be left aligned in one column
  and their results right aligned in a 2nd column

Change-Id: I3429d6092f2bd5d5f6825245f5439ace3f47f1fa
Reviewed-on: https://chromium-review.googlesource.com/360653
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agokevin / gru: Increase size of code RAM
Shawn Nematbakhsh [Tue, 26 Jul 2016 20:07:13 +0000 (13:07 -0700)]
kevin / gru: Increase size of code RAM

Reduce size of UART Tx buffer to 1024 bytes on all npcx platforms and
increase size of code memory by 6K bytes on Kevin.

BUG=chrome-os-partner:52876
BRANCH=None
TEST=`make buildall -j` with subsequent commit.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib9e52a4406f84cfc434984f8819d7ef02b70beb4
Reviewed-on: https://chromium-review.googlesource.com/363591
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agotcpm: fusb302: Changed get_cc to use full manual mode for revB
Scott [Tue, 19 Jul 2016 21:37:35 +0000 (14:37 -0700)]
tcpm: fusb302: Changed get_cc to use full manual mode for revB

The FUSB302A had silicon limitation that required using its
autodetect logic when presenting as a SRC. While testing on
Kevin/Gru and connecting PD dongles, observed issues where
following successful connects, the USB PD state machine would
remain in SRC_DISCONNECTED state after removing the dongle.
Flipping the connector (to reverse polarity) will recover from
this stuck state.

In order to resolve this problem and to make the tcpm_get_cc()
FUSB302 driver function more consistent with the USB PD protocol
state machine while acting as a source, the autodetect feature
is now only used when a revA silicon device is detected.

If it's not revA, then full manual mode is utilized for tcpm_get_cc.
In addition, a new measure_cc_pin_source funciton was added
that consolidates the operations that are shared between both
autodetect and manual modes.

BUG=chrome-os-partner:55429
BRANCH=None
TEST=Manual
Connected display adapter dongles and TypeC hub dongle repeatedly
and verified that each connect attempt resulted in the USB PD
state machine getting to SRC_READY state. Never observed the
error state described above which previously could be repeated
within ~ < 10 connection attempts.

Change-Id: I3c8c6990129e0f1555a6698574adc603d6b7b45b
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361617
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agocr50: process retry counter and act on it
Vadim Bendebury [Sun, 24 Jul 2016 00:02:18 +0000 (17:02 -0700)]
cr50: process retry counter and act on it

A recent cr50 loader modification introduced a counter in a scratch
register which is incremented on every startup. The idea is that valid
RW would decrement the counter, signaling that the start was
successful.

Should the counter exceed the value of 5, the loader assumes that the
RW being started is not fit to run, and picks the older RW to run, if
available.

This patch adds a function to process the startup retry counter.

First of all the counter is zeroed, as this function is supposed to be
called only once the RW run is considered successful and reliable.

Then the current situation is examined. If the counter value read from
the scratch register exceeds 5 AND running image is not the newer of A
and B, it is considered an indication of a fallback from a bad newer
image.

To prevent the newer image from being considered a contender on the
following startups, its header is corrupted.

BRANCH=none
BUG=chrome-os-partner:55151, chrome-os-partner:55667

TEST=modified code for testing purposes, by adding a call to
    system_process_retry_counter() to tpm_task() after line 534, which
    would cause the new function to be called soon after boot.

    built a new image and installed it on the debug board. Then
    modified the image to throw an exception early in the boot up
    sequence, and installed it as a newer image on the debug board.

    Observed the debug board restart the new image several time and
    then fall back to the older image, printing the following on the
    console:

system_process_retry_counter:retry counter 7
corrupt_other_header: RW fallback must have happened, magic at 44000 before: ffffffff
corrupt_other_header: magic after: 0

   The following restarts start the older image without trying to run
   the failing newer image.

Change-Id: Ia7497401e38fe2c3957af910cf745e45da985245
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362776
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agocts: Move C flags to cts/build.mk
Daisuke Nojiri [Mon, 25 Jul 2016 23:09:21 +0000 (16:09 -0700)]
cts: Move C flags to cts/build.mk

We should separate global Makefile from CTS stuff as much as possible.
This makes reading and chaging code simpler.

BUG=none
BRANCH=none
TEST=make buildall

Change-Id: If9e99e0e9b660707b1e22f2362bd6f782930dc09
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Chris Chen <twothreecc@google.com>
4 years agokevin / gru: Add psys console command
Shawn Nematbakhsh [Mon, 25 Jul 2016 22:19:10 +0000 (15:19 -0700)]
kevin / gru: Add psys console command

Add `psys` console command for system power monitoring. Note that pmon
resistor / cap are not stuffed by default.

BUG=chrome-os-partner:55616
BRANCH=None
TEST=Verify `psys` command on kevin prints a result.

Change-Id: I9ac7b55ad30d0709624f94c27e173eb80f80a1ac
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363061
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agog: Improve version info for dual RO & RW images
Bill Richardson [Mon, 25 Jul 2016 06:58:05 +0000 (23:58 -0700)]
g: Improve version info for dual RO & RW images

The SoC looks for two RO images at reset, and is typically
configured for two RW images as well. This CL reports version
strings for all those images, as well as identifying the active
RO and RW copies.

Since the RO image doesn't contain a version string, we create
one using the epoch_, major_, minor_, and img_chk_ members of its
signed header.

BUG=chrome-os-partner:55558
BRANCH=none
TEST=make buildall; run on Cr50 hardware

The "version" command now includes information like this:

  RO_A:  * 0.0.2/a3c3d5ea
  RO_B:    0.0.2/8895c9eb
  RW_A:    cr50_v1.1.4965-a6c1c73-dirty
  RW_B:  * cr50_v1.1.4959-2f49d5c

The '*' indicates the active image.

The test/tpm_test/tpmtest.py program has been updated to request
the version information at startup, and it also now reports
similar information, just all on one line:

  RO_A:* 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1 ...

The active images are marked with a '*' following the ':', so
that the same regexp can match either format:

  ($ro, $rw) = m/RO_[AB]:\s*\*\s+(\S+).*RW_[AB]:\s*\*\s+(\S+)/s;

Change-Id: Ic27e295d9122045b2ec5a638933924b65ecc8e43
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362861
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agocharge_manager: Treat soft-disconnected batteries as not present
Shawn Nematbakhsh [Mon, 25 Jul 2016 23:17:05 +0000 (16:17 -0700)]
charge_manager: Treat soft-disconnected batteries as not present

For the purpose of spoofing dual-role capability, treat
soft-disconnected batteries as not present, since they are not capable
of supplying a current until they are revived.

BUG=chrome-os-partner:55617
BRANCH=None
TEST=Manual on kevin w/ subsequent CL. Put battery into soft-disconnect
state. Attach charger and verify EC doesn't lose power and battery again
supplies current.

Change-Id: Ie6b83b3d4e1e33c4bbbd1a90450506e7dcd1dfb2
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363003
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
4 years agotcpm: fusb302: Set VCONN appropriately when enabled
Shawn Nematbakhsh [Mon, 18 Jul 2016 22:54:01 +0000 (15:54 -0700)]
tcpm: fusb302: Set VCONN appropriately when enabled

VCONN must be enabled separately when a CC line is selected for
communication.

BUG=chrome-os-partner:55383
BRANCH=None
TEST=Manual on kevin. Insert DP dongle, verify we enter SRC_READY state.

Change-Id: I8bb8de2cb2faedcd7eafc931da7a0137b6b41018
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361530
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
4 years agocharge_state_v2: Add console command to test discharge on AC
Vijay Hiremath [Fri, 22 Jul 2016 21:43:41 +0000 (14:43 -0700)]
charge_state_v2: Add console command to test discharge on AC

Added support to test discharge on AC using console command.

BUG=chrome-os-partner:55572
BRANCH=none
TEST=Manually tested on Reef.
     "chgstate discharge on"  - Battery is discharging
     "chgstate discharge off" - Battery is charging

Change-Id: I07733fe28d22b0ad6e3bd172a445e43a60650762
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/362678
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agocharge_state_v2: BD99955: Do not inhibit charge in battery learn mode
Vijay Hiremath [Thu, 21 Jul 2016 06:05:28 +0000 (23:05 -0700)]
charge_state_v2: BD99955: Do not inhibit charge in battery learn mode

BD99955 charger auto exits from the battery learn mode if the charge
is inhibited. Hence, do not inhibit the charger in battery learn mode.

BUG=chrome-os-partner:55491
BRANCH=none
TEST=Manually tested on Reef using 'ectool chargecontrol' command.
     Able to enter/exit battery learn mode safely.

Change-Id: If05f9a9451842b77619e0a8c5db5e54fec24f399
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/362123
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agocharger: bd99955: Remove incorrect VSYSVAL_THL / THH settings
Shawn Nematbakhsh [Mon, 25 Jul 2016 20:20:56 +0000 (13:20 -0700)]
charger: bd99955: Remove incorrect VSYSVAL_THL / THH settings

VSYSVAL_THL / THH are high / low hysteresis values below which dead
battery condition is triggered, which doesn't match our register
configuration. Leave these regs at default for now until we better
understand the effect of dead battery detection.

BUG=chrome-os-partner:55626
BRANCH=None
TEST=Manual on kevin with other pending changes, verify dead battery
successfully charges.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I35a44dd0005f165f17073e8b0f2fd5dca1eda856
Reviewed-on: https://chromium-review.googlesource.com/363030
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agocharger: bd99955: Adjust VSYS based on fast vs precharge state
Shawn Nematbakhsh [Thu, 21 Jul 2016 21:59:00 +0000 (14:59 -0700)]
charger: bd99955: Adjust VSYS based on fast vs precharge state

Rohm suggests setting VSYS to the higher value during precharge and only
setting it to the lower voltage after we have crossed the lower voltage.
Note that the VSYS register also controls the pre vs fastcharge
threshold, so setting VSYS to the lower voltage essentially enables
fastcharge.

BUG=chrome-os-partner:55524
BRANCH=None
TEST=Manual on kevin, verify dead battery is able to charge through
precharge to fastcharge.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia5b953c8dfbb25970ab329d5487a317ad37ba609
Reviewed-on: https://chromium-review.googlesource.com/362442
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agog: Remove unused GC_REVISION compile-time constant
Bill Richardson [Sun, 24 Jul 2016 23:24:19 +0000 (16:24 -0700)]
g: Remove unused GC_REVISION compile-time constant

This constant is not used anywhere, so we don't need to specify it.

BUG=none
BRANCH=none
TEST=buildall; try on Cr50

Change-Id: I82fef5d3172ec7d5a781405c8e66f74af49ed172
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362852
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agog: report proper silicon version
Vadim Bendebury [Sat, 23 Jul 2016 18:28:39 +0000 (11:28 -0700)]
g: report proper silicon version

There are two g chip versions in circulation currently, B1 and B2.
Make the 'version' command properly report it.

BRANCH=none
BUG=none
TEST=verified that both B1 and B2 report versions properly

Change-Id: I1c5b9f0da0170cda2c636b857e92b9d3de165422
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362643
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agotpm: remove int_status variable
Vincent Palatin [Wed, 20 Jul 2016 14:42:45 +0000 (16:42 +0200)]
tpm: remove int_status variable

It doesn't seem to be used anywhere,
so let's remove it rather than having to re-initialize it.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:52366
TEST=make BOARD=cr50

Change-Id: I08175621fe26a4344ce1716a83ad4233531043a1
Reviewed-on: https://chromium-review.googlesource.com/361940
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agoinclude: Add HCI include files from NewBlue
Myles Watson [Tue, 27 Jan 2015 20:15:58 +0000 (12:15 -0800)]
include: Add HCI include files from NewBlue

Copied with permission from Dmitry Grinberg, the original author.

Add HCI_SUCCESS, some minor fixes.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ia4f6f0d092674fca1297e94a16edbc14399d2c63
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362348
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
4 years agoCR50: add endorsement certificate flow
nagendra modadugu [Fri, 22 Jul 2016 02:36:28 +0000 (19:36 -0700)]
CR50: add endorsement certificate flow

This change implements logic for installing
endorsement certificates in the RW section.

The endorsement certificates are initially
provisioned in a fixed RO flash region and
are copied in the RW TPM data region (once
this region has been initialized).

Also add code for reading from the info bank,
which is where the endorsement seed is
initially stored.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=TCG tests running

Change-Id: Id8c16d399202eee4ac0c4e397bdd29641ff9d2f3
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/362402
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agonrf51: Make timer handling names more obvious
Myles Watson [Thu, 26 Feb 2015 19:40:44 +0000 (11:40 -0800)]
nrf51: Make timer handling names more obvious

There are three timers, each with four capture/compare (CC)
registers.  The timer code uses 3 CC registers from one timer.

Use macros for the defines, so that it is more obvious which
timer and which register are being used.

TEST=make BOARD=hadoken
BRANCH=NONE
BUG=None

Change-Id: Icb058d9717800a87b394270eef38a3a744a13b7d
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361793
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
4 years agohostcmd: Flush UART before doing cold reboot
Shawn Nematbakhsh [Fri, 22 Jul 2016 21:19:32 +0000 (14:19 -0700)]
hostcmd: Flush UART before doing cold reboot

Flush our UART buffer to ensure that we don't miss prints when we reboot
the EC.

BUG=chrome-os-partner:55539
BRANCH=None
TEST=Manual on kevin, issue cold reboot host command, verify that
"Executing host reboot command" is seen on console.

Change-Id: I96d5687b413ba4f603e3e7845b5cbba1c2d65efa
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agokevin / gru: Warn users when incompatible GPIO config is used
Shawn Nematbakhsh [Fri, 22 Jul 2016 18:41:36 +0000 (11:41 -0700)]
kevin / gru: Warn users when incompatible GPIO config is used

Old kevin / gru boards are no longer supported by our current GPIO
configuration and must revert a CL to boot properly. Detect if old
boards are used with an incompatible config and warn users of this fact
by spamming the EC console and blinking the LED red.

BUG=chrome-os-partner:55561
BRANCH=None
TEST=Boot new kevin, verify no console spam or LED blinkage is seen. Verify
old kevin + old gru spam the console and blink LED.

Change-Id: I6d49720f760a6bef2bb3db6872857a5f61259e06
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362653
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agotpm: report correct fw version
Vadim Bendebury [Mon, 11 Jul 2016 20:47:41 +0000 (13:47 -0700)]
tpm: report correct fw version

The tpm firmware version register should report the current RW image's
version, not the RW_A.

BRANCH=none
BUG=chrome-os-partner:55145
TEST=verified that tpm firmware version reported by coreboot on the AP
     console matches the version running on the device, for both RW_A
     and RW_B.

     From coreboot console log on two different runs:

  Firmware version: RO: 84e2dde7 RW: cr50_v1.1.4943-f81a901
  Firmware version: RO: 84e2dde7 RW_B: cr50_v1.1.4943-f81a901

Change-Id: I43f5432e44e38dbf9b42750dd2042a0f005bcbfb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362612
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoCr50: Rearrange flash to allow dual RO images
Bill Richardson [Fri, 22 Jul 2016 01:34:06 +0000 (18:34 -0700)]
Cr50: Rearrange flash to allow dual RO images

We had been putting the NVMEM flash where the boot rom would
expect to find RO_B, preventing us from ever being able to update
the bootloader.

With this CL, we're rearranging the flash to support both RO_A
and RO_B. The current flash layout now looks like this:

  0x40000 RO_A
  0x44000 RW_A
  0x7c000 TOP_A
  0x80000 RO_B
  0x84000 RW_B
  0xbc000 NVMEM
  0xbffff <end of flash>

BUG=chrome-os-partner:44803
BRANCH=none
TEST=make buildall, also manual tests on Cr50 boards

First, check that our current process still works:

  make BOARD=cr50 CR50_RO_KEY=cr50_rom0-dev-blsign.pem.pub
  spiflash -i -v build/cr50/ec.hex

  Yep, it does, but that only produces RO_A, not RO_B.

To test the dual RO behavior, I used prebuilt RO_A and RO_B blobs
for the bootloaders, signed using Marius' new scheme.

Build the unsigned image, then sign it using Vadim's scripts:

  make BOARD=cr50 -j30
  ~/bin/bs hex

We'll garble various bits of the full image to invalidate each of
the four RO/RW/A/B parts.

Find lines common to both ROs and common to both RWs:

  sort B1*.hex | uniq -c | grep ' 2 ' | \
       awk '{print $2}' | sort > tmp.ro2
  sort build/cr50/RW/ec.RW*.signed.hex | uniq -c | grep ' 2 ' | \
       awk '{print $2}' | sort > tmp.rw2
  ro=$(diff tmp.ro2 tmp.rw2 | grep '<' | head -1 | awk '{print $2}')
  rw=$(diff tmp.ro2 tmp.rw2 | grep '>' | head -1 | awk '{print $2}')

Double-check to be sure we don't have any false matches:

 grep -l $ro build/cr50/RW/ec.RW*.signed.hex B1_*.hex
 grep -l $rw build/cr50/RW/ec.RW*.signed.hex B1_*.hex

The pre-signed RO_A image is older than RO_B, but both have the
same epoch/major/minor, which is all that the bootrom checks for.
It doesn't look at the timestamp.

The RW_A is older than RW_B because of the sequential signing
process. The RO bootloaders will check their timestamp, so RW_B
should be preferred.

RO_A  RO_B  RW_A  RW_B
good  good  good  good

  cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex
  spiflash -v -i foo.hex

    jump @00040400
    jump @00084000

  => boots RO_A -> RW_B

RO_A  RO_B  RW_A  RW_B
good  good  good  bad

  cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex

  ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}')
  sed -i "${ln}d" foo.hex

  spiflash -v -i foo.hex

    jump @00040400
    jump @00044000

  => boots RO_A -> RW_A

RO_A  RO_B  RW_A  RW_B
bad   good  good  good

  cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex

  ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}')
  sed -i "${ln}d" foo.hex

  spiflash -v -i foo.hex

    jump @00080400
    jump @00084000

  => boots RO_B -> RW_B

RO_A  RO_B  RW_A  RW_B
bad   good  good  bad

  cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex

  ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}')
  sed -i "${ln}d" foo.hex

  ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}')
  sed -i "${ln}d" foo.hex

  spiflash -v -i foo.hex

    jump @00080400
    jump @00044000

  => boots RO_B -> RW_A

Yay.

Now make sure RW_A and RW_B can be updated using usb_updater.

  \rm -rf build
  make BOARD=cr50 -j30
  ~/bin/bs

  ./extra/usb_updater/usb_updater build/cr50/ec.bin

  I'm running RW_A, it updates and reboots into RW_B. Good.

  reboot 5 times, and it reverts to RW_A.

  Power cycle and it goes to RW_B again.

Update to RW_A.

  \rm -rf build
  make BOARD=cr50 -j30
  ~/bin/bs

  ./extra/usb_updater/usb_updater build/cr50/ec.bin

  I'm running RW_B, it updates and reboots into RW_A. Good.

  reboot 5 times, and it reverts to RW_B.

  Power cycle and it goes to RW_A again.

Cool.

Change-Id: I6c1689920de06c72c69f58ad2ef1059d9ee0d75f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362521
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoconsole: Protect more consoles with CONFIGs
Myles Watson [Fri, 22 Jul 2016 00:00:32 +0000 (17:00 -0700)]
console: Protect more consoles with CONFIGs

BUG=None
BRANCH=None
TEST=make buildall -j32

Space is limited, and having just the consoles which are active
makes debugging easier.

Change-Id: I0e519a54c12ba0b861ff4e75aa03b7483d4544c7
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362580
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
4 years agoflash_ec: Add support for flashing using CCD
Mary Ruthven [Fri, 13 May 2016 20:03:48 +0000 (13:03 -0700)]
flash_ec: Add support for flashing using CCD

When a kevin, gru, or reef are attached to the host machine using a
suzyQ, they can use CCD to update the AP or EC using flashrom. To use
suzyQ you have to specify raiden_debug_spi as the flashrom programmer.
This change adds support to flash_ec for using the right programmer to
update with CCD over suzyQ instead of servo.

BUG=chrome-os-partner:50701, chrome-os-partner:50712
BRANCH=none
TEST=make sure "util/flash_ec --BOARD=kevin --raiden" updates the EC
when CCD is enabled

Change-Id: Ie63337b9689c68aa60163d7e54c5ebefa97b4e21
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344427
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agobd99955: Add function for reading temperature
David Hendricks [Fri, 15 Jul 2016 01:56:26 +0000 (18:56 -0700)]
bd99955: Add function for reading temperature

BUG=chrome-os-partner:54818
BRANCH=none
TEST=needs testing

Change-Id: I3a33f79e7d57e6f94731a7d929dbcd083e0f1ca1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360721
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
4 years agoreef: Introduce IS_PROTO hack
David Hendricks [Sat, 16 Jul 2016 00:27:44 +0000 (17:27 -0700)]
reef: Introduce IS_PROTO hack

This will be used to hack around code that only works on proto.
The earlier method of attempting to use board ID to determine
codepath worked to a limited extent, but fell short due to pin
swappings. So the dream of having a single binary that would work
on multiple board revisions died, and now if someone wants to build
for an old proto board they need to set this #define to 1.

BUG=chrome-os-partner:54947
BRANCH=none
TEST=tested with upcoming patches in this series

Change-Id: I5468c252e5401d69b108c75fa00b3dfbbcf77c22
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360949
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agoCr50: NvMem: Modified nvmem_init to handle 2 corrupt partitions
Scott [Fri, 22 Jul 2016 02:17:16 +0000 (19:17 -0700)]
Cr50: NvMem: Modified nvmem_init to handle 2 corrupt partitions

During initialization the NvMem module looks for either a valid
partition or that the NvMem area is fully erased. If neither of
these two conditions were found, then it was only returning an
error code and logging a message to the console.

This CL modifies nvmem_init() so that if the error case as described
above is detected, then it will call nvmem_setup() which will
create two valid partitions. In addition, the setup function
erases all of the existing data in the NvMem space.

Enhanced the unit test that deals with both partitions being
corrupted so that it verifies the version numbers are correct
and that all user buffer data is set to 0xff.

BUG=chrome-os-partner:55536
BRANCH=None
TEST=Manual
Executed make runtests TEST_LIST_HOST=nvmem and verifed that all
tests passed.

Change-Id: Ib932e02f15bd1aad7811032a12d826c76476e53f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362448
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoconsole: Add a console for Bluetooth LE
Myles Watson [Thu, 18 Dec 2014 01:11:04 +0000 (17:11 -0800)]
console: Add a console for Bluetooth LE

Protect the console with CONFIG_BLUETOOTH_LE to save space.

BUG=None
BRANCH=None
TEST=make buildall -j32

Change-Id: I2309bf953904af36684b0fe32f94b2254b13c6a4
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361536
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
4 years agog: deactivate the PHY during usb_release
Mary Ruthven [Fri, 22 Jul 2016 00:06:34 +0000 (17:06 -0700)]
g: deactivate the PHY during usb_release

The USB controller should disable the PHY itself when usb is released,
but from the power tests I ran it does not. This change adds a call in
usb_release to deactivate the PHY.

It looks like having the AP on vs off also makes a difference in power
consumption. I am looking into that now, but until that is resolved turn
of the AP off while testing this USB change to see the effects on power.

BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
Without deactivating the PHY put cr50 into deep sleep on gru.
run 'reboot ap-off'
measure pp3300_haven_mw and it is around 4.5mW
Add deactivating the PHY during usb_release.
Put cr50 into deep sleep
run 'reboot ap-off'
measure the power and the average should be around 2mW

Change-Id: I16e6885a4e40c78e81d9bbc42c9af79e5f55047e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362159
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoupgrade_fw: fw_upgrade_command_handler: fix cmd_size check
Lucian Cojocar [Wed, 20 Jul 2016 17:34:04 +0000 (10:34 -0700)]
upgrade_fw: fw_upgrade_command_handler: fix cmd_size check

body_size is unsigned so the comparison was always false

BUG=None
BRANCH=none
TEST=tested the update process on CR50 board using the usb_updater

Change-Id: I004ee94653656449ae6f8699f06422e925d9e1b6
Signed-off-by: Lucian Cojocar <cojocar@google.com>
Reviewed-on: https://chromium-review.googlesource.com/362082
Commit-Ready: Dan Shi <dshi@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoservo_v4: add python firmware update script
Nick Sanders [Tue, 19 Jul 2016 22:36:16 +0000 (15:36 -0700)]
servo_v4: add python firmware update script

This script is more flexible for updating multiple targets,
including servo_v4, servo_micro, and sweetberry.

The command takes a json config file that specifies
flash layout, USB ID, and size.

BUG=chromium:571476
TEST=./fw_update.py -b servo_v4.json -f ec.bin; both RW, RO
BRANCH=none

Change-Id: Ic9dcee2c23484bb28c8bfaf1882c578314534116
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361835
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agoservo_v4: add USB updater
Nick Sanders [Tue, 19 Jul 2016 22:27:22 +0000 (15:27 -0700)]
servo_v4: add USB updater

This adds a Google FW update endpoint to
servo v4.

BUG=chromium:571476
TEST=successfully update servo v4 via usb
BRANCH=None

Change-Id: I79cb46364d416300e430708db25814f861a6d7c9
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361833
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agoservo_micro: add USB updater
Nick Sanders [Tue, 19 Jul 2016 22:33:47 +0000 (15:33 -0700)]
servo_micro: add USB updater

This adds a Google FW update endpoint to
servo micro in place of a GPIO enpoint.

BUG=chromium:571477
TEST=successfully update servo micro via usb
BRANCH=None

Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I3d6c501d515b3f1db6e8259fbb829abe18f72e00
Reviewed-on: https://chromium-review.googlesource.com/361834
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agotimer: fix clock() implementation to match TPM2 library expectations
nagendra modadugu [Mon, 18 Jul 2016 03:50:45 +0000 (20:50 -0700)]
timer: fix clock() implementation to match TPM2 library expectations

The clock() function was introduced to provide free running clock for
the TPM2 library, which expects this clock to run with a millisecond
resolution.

This patch fixes the bug where the function in fact was returning the
clock running at a microsecond resolution.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=with the appropriate modification of the user of this function
      all lockout related TCG tests pass.

Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361180
(cherry picked from commit b4e78b309900402499b8742199fb4536570d3000)
(cherry picked from commit fefaa02a4f2c807a3ad50137bd7dba7f5f081c31)
Change-Id: Ic02fffca610426d22e58609eb8c3693aec96ad5c
Reviewed-on: https://chromium-review.googlesource.com/362118

4 years agoCR50: when testing an RSA key, check that N % p == 0
nagendra modadugu [Sun, 17 Jul 2016 16:47:20 +0000 (09:47 -0700)]
CR50: when testing an RSA key, check that N % p == 0

TCG test CPCTPM_TC2_2_22_02_08 installs an RSA key
for which p does not divide the modulus, and subsequently
the test is expected to fail accordingly.

This change adds the check necessary to pass this test --
a check that p divides N.

Also removed dangling function declaration for bn_mul().

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=TCG test CPCTPM_TC2_2_22_02_08 passes consistently

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360968
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit c4430ecac8f77a05ac4071679de1535e0da2779e)
(cherry picked from commit 832d04b5b8cebf702d2ec00051615f827d2d16e1)
Change-Id: If2ffc6260ae848d75e93263a37e84f0ed7d301a0
Reviewed-on: https://chromium-review.googlesource.com/362117
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoCR50: do not try searching in uninitialized TPM NV RAM.
Vadim Bendebury [Sun, 17 Jul 2016 01:14:02 +0000 (18:14 -0700)]
CR50: do not try searching in uninitialized TPM NV RAM.

The manufacturing status check verifies if the proper certificates are
found in the device NV RAM. This check can not succeed unless NV RAM
metadata is initialized by calling _TPM_Init().

If the check shows that the device has not been through manufacturing
sequence yet, TPM_Manufacture() needs to be invoked to make sure that
all relevant TPM structures are initialized and properly stored in NV
RAM. _TPM_Init() needs to be invoked again after that.

BRANCH=ToT
BUG=chrome-os-partner:43025
TEST=restarting Kevin device with pre-manufactured CR50 takes it
     through factory initialization on every reboot. Restarting Kevin
     once TPM is through manufacturing process shows that the
     previously saved rollback counters are preserved.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361093
Reviewed-by: Nagendra Modadugu <ngm@google.com>
(cherry picked from commit 61a0fe734e808d1dbdf56fb6023e04adf66553b3)
(cherry picked from commit 3207a57fb2f5957b6e833d9ab1f9ea46021c5e1e)
Change-Id: I80b69f2c4b8d0e4cca154db510867df39c707ce2
Reviewed-on: https://chromium-review.googlesource.com/362084

4 years agotpm: add manufacturing status check
Vadim Bendebury [Thu, 21 Jul 2016 14:14:12 +0000 (07:14 -0700)]
tpm: add manufacturing status check

For now the presence of both RSA and EC certificates at fixed NVRAM
indices is considered evidence of TPM being through manufacturing.

BRANCH=none
BUG=chrome-os-partner:50645
TEST=with the rest of the patches applied TPM manufacturing status is
     properly detected at startup.

Change-Id: Iff3861603272cdfb58ebc523458c114685b2429f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362351
Reviewed-by: Marius Schilder <mschilder@chromium.org>
4 years agoCR50: match private key against certs on endorsement
nagendra modadugu [Thu, 14 Jul 2016 22:49:34 +0000 (15:49 -0700)]
CR50: match private key against certs on endorsement

This change updates the ecc and rsa key generation templates.

Due to crosbug.com/p/55260 in which the TPMT_PUBLIC template is
truncated during personalization, ecc generation requires a
workaround.

For RSA, allow the standard template to be used even on development
builds.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360441
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit db5a1ca8a40be9bf7e741637cd8d7f15f520ab11)
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit b6620239bb7c4f5900051677f40f161c0a853a94)
Change-Id: I1af83f1ec86e7ee4d325a4b7aabe03ce08c4108b
Reviewed-on: https://chromium-review.googlesource.com/362142
Reviewed-by: Nagendra Modadugu <ngm@google.com>
4 years agoCR50: fix uninitialized buffer size in _cpri__SignRSA
nagendra modadugu [Sat, 16 Jul 2016 04:29:54 +0000 (21:29 -0700)]
CR50: fix uninitialized buffer size in _cpri__SignRSA

The TPM2 wrapper library does not initialize the
size of an output buffer length prior to calling
into cr50/tpm2.  This results in arbitrary failures
depending on memory layout.

Force the buffer length unseen, though this should
be fixed in the TPM2 library.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow
TEST=CPCTPM_TC2_2_20_02_03 passes, which was consistently failing

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360908
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 635cb7ada25e76e504087916364e2db08a2133ab)
Change-Id: I90e9b4d76986ffa27acc944e48afc2efaadad7cd
Reviewed-on: https://chromium-review.googlesource.com/362116
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoCR50: when generating primes, check compatibility with exp
nagendra modadugu [Thu, 14 Jul 2016 22:50:42 +0000 (15:50 -0700)]
CR50: when generating primes, check compatibility with exp

Primes generated for RSA keys need to hold the following
property (public_exponent mod p) > 1 in order for the
private exponent to exist.  This change adds this check
for the public exponent RSA_F4 (65537).

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360662
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@google.com>
(cherry picked from commit 1c37f84ae7fae9f5841421447c7f235790ab6a93)
(cherry picked from commit b2c1678b27c79a2c93f5519e00161243fa0a5d88)
Change-Id: I87bd898cc3750bf1e492bc263edb6eac1edf2a17
Reviewed-on: https://chromium-review.googlesource.com/362115
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoCR50: bn_modinv_vartime - don't reduce on carry condition
nagendra modadugu [Thu, 14 Jul 2016 12:33:57 +0000 (05:33 -0700)]
CR50: bn_modinv_vartime - don't reduce on carry condition

The modinv logic shouldn't reduce modulo MOD
on a carry condition.  Instead, just use more
space to hold the carry bit.

Also use full size buffers for all variables.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115
TEST=unit tested

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360248
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 3f4e131daef04db5c990bb4532bb67ee9e58c02b)
(cherry picked from commit 485b02a17ecdd3c52210fd90ff29b4f1b829a47a)
Change-Id: I8d4f78966bfe15f0739c9de23f5a12685a65aabb
Reviewed-on: https://chromium-review.googlesource.com/362113
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agoCR50: rename struct BIGNUM -> struct LITE_BIGNUM
nagendra modadugu [Thu, 14 Jul 2016 09:59:05 +0000 (02:59 -0700)]
CR50: rename struct BIGNUM -> struct LITE_BIGNUM

The name BIGNUM collides with a namesake struct
in openssl.  It would be convenient to write
test code that compares results between openssl
and dcrypto, hence this rename.

Also rename some #defines that conflict with
openssl names.

CQ-DEPEND=CL:*270476
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115
TEST=build succeeds

Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360346
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a15b495497728a6b212bd87e92f6ba5ba463f985)
Change-Id: Ic53ce805cfcc591c68fbc1ef90ff2f92cec973a6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362112
Reviewed-by: Nagendra Modadugu <ngm@google.com>
4 years agocts: Added file to list error codes as integers
Chris Chen [Mon, 11 Jul 2016 21:52:05 +0000 (14:52 -0700)]
cts: Added file to list error codes as integers

BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th
  and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results print their test name followed
  by a space and and integer error code

Change-Id: If52e9b50705779b3a291e2d0f6b0721a5b6197d8
Reviewed-on: https://chromium-review.googlesource.com/359988
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
4 years agoectool: Fix incorrect fan numbers from ectool
Divya Sasidharan [Fri, 8 Jul 2016 17:03:58 +0000 (10:03 -0700)]
ectool: Fix incorrect fan numbers from ectool

Return 0 if the board does not need fan indicated
by EC_FEATURE_PWM_FAN.

BRANCH=None
BUG=chrome-os-partner:55090
TEST=make buildall -j;
     in reef command "ectool pwmgetnumfans" returns 0

Change-Id: I7b59d266532622607c61fe3e7dd1bd0cc8ea9766
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359069
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agoservo_v4: copypasta usb updater code into common
Nick Sanders [Tue, 19 Jul 2016 22:13:50 +0000 (15:13 -0700)]
servo_v4: copypasta usb updater code into common

This copies the generic USB update code into common
so it can be used on other platforms. There should be
no functional change. cr50 folks want no change to their
code so vbendeb@chomium.org will refactor this back
together at a later date.

BUG=chromium:571476
TEST=none
BRANCH=none

Change-Id: I710afb22940013e7db5d8694898b90c0ae245777
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agoCR50: add a #define guard to enable use of non-asm bignum
nagendra modadugu [Thu, 14 Jul 2016 10:42:54 +0000 (03:42 -0700)]
CR50: add a #define guard to enable use of non-asm bignum

Bignum test code that runs on host (e.g. x86) can't
make use of CR50 assembly; add a #define switch which
allows for host builds.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds

Reviewed-on: https://chromium-review.googlesource.com/360247
Commit-Queue: Nagendra Modadugu <ngm@google.com>
Trybot-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 20158b1bc5a80812dde7b798296a8b6e5dcc8400)
(cherry picked from commit 4b34af801fd565fe8fc2b855307ba5a7074b3470)
Change-Id: Ia754fd47e958e8338cd4cee60405305e58b8aa88
Reviewed-on: https://chromium-review.googlesource.com/362114
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
4 years agotpm: fire watchdog before executing commands
Vadim Bendebury [Thu, 14 Jul 2016 01:25:12 +0000 (18:25 -0700)]
tpm: fire watchdog before executing commands

In certain test scenarios the tpm task is hogging all resource and
causes watchdog resets. Let's kick the watchdog in every loop, Long
calculations already have watchdog kicking in place.

BRANCH=ToT
BUG=none
TEST=tests executed in rapid succession do not cause watchdog resets
     any more.

(cherry picked from commit de8fb11bfd07d3fea2048b6848b8a183c31e2580)
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360229
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Change-Id: Ifaad6f9b4af2218f601412a36a075b4b4275d56f
Reviewed-on: https://chromium-review.googlesource.com/362170

4 years agocheckpatch: prevent stupid complaints about description title
Vadim Bendebury [Thu, 21 Jul 2016 16:24:33 +0000 (09:24 -0700)]
checkpatch: prevent stupid complaints about description title

Let's not force the linux kernel description format on cherry picked
patchs, especially since this check sometimes gets false positive, and
since this formwat is not used in the ec codebase.

BRANCH=none
BUG=none
TEST=no more annoying error reports on cherry-picked patches

Change-Id: I903bb87c48998932bc9308245d158f212a57fdd1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362074
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
4 years agoCR50: clear SHA config register when initializing
nagendra modadugu [Fri, 8 Jul 2016 02:46:41 +0000 (19:46 -0700)]
CR50: clear SHA config register when initializing

The SHA config register should be cleared, so that
only required bits are set on init().

Doing so ensures that previous settings that used
the engine in a different mode, e.g HMAC, do not
survive.

BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds; tpmtest.py tests pass; manufacture works

(cherry picked from commit 9b3619ddd7304359ee17e243923f1e47c925cb21)
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/359418
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: If5a79af06ea7512f19775a2f34d741b144f211f7
Reviewed-on: https://chromium-review.googlesource.com/358982
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>

4 years agoboard/reef: enable CONFIG_CHIPSET_RESET_HOOK
Aaron Durbin [Wed, 20 Jul 2016 18:51:30 +0000 (13:51 -0500)]
board/reef: enable CONFIG_CHIPSET_RESET_HOOK

In order for the vstore to be unlocked one needs to enable
the CHIPSET_RESET_HOOK. Do that for reef.

BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.

Change-Id: I94a41a08ad8649423988372607835da01ec12b8b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362001
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agochip/npcx: interrupt on both edges of PLTRST_L
Aaron Durbin [Wed, 20 Jul 2016 18:47:01 +0000 (13:47 -0500)]
chip/npcx: interrupt on both edges of PLTRST_L

Different actions need to be taken on PLTRST_L depending on
if it is asserted or deasserted. The vstore module needs to
reset its locks when PLTRST_L is asserted (host is in reset).
The interrupt was previously on occurring on a deassertion of
PLTRST_L (rising edge). That's not conducive for handling
actions which are required for assertion (falling edge).
Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be
called when PLTRST_L is asserted.

BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.

Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362000
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agostm32: add generic stream interface for stm32
Nick Sanders [Tue, 19 Jul 2016 22:21:49 +0000 (15:21 -0700)]
stm32: add generic stream interface for stm32

usb-stream is used by USB updater as well as uart
forwarding. Add parameter for custom USB class define.

BUG=chromium:571476
TEST=builds
BRANCH=none

Change-Id: Id6294709de0c5408b10ed366b261be1bc7da7767
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361832
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
4 years agotcpm: anx74xx: Add alert polarity member to tcpc_config_t
David Hendricks [Sat, 16 Jul 2016 02:38:20 +0000 (19:38 -0700)]
tcpm: anx74xx: Add alert polarity member to tcpc_config_t

This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.

BUG=none
BRANCH=none
TEST=built and booted on reef

Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
4 years agork3399: Transition to / from S3 based upon GPIO_AP_EC_S3_S0_L
Shawn Nematbakhsh [Tue, 14 Jun 2016 22:05:35 +0000 (15:05 -0700)]
rk3399: Transition to / from S3 based upon GPIO_AP_EC_S3_S0_L

BRANCH=None
TEST=Set GPIO_AP_EC_S3_S0_L high from sysfs, verify EC power state
machine enters S3.
BUG=chrome-os-partner:54328
CQ-DEPEND=CL:*270114

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0fbd49775c245f3d747ddb46801ed89085829e12
Reviewed-on: https://chromium-review.googlesource.com/352651
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
4 years agonpcx: shi: Properly mux pins as GPIO when disabling SHI
Shawn Nematbakhsh [Thu, 21 Jul 2016 00:59:34 +0000 (17:59 -0700)]
npcx: shi: Properly mux pins as GPIO when disabling SHI

MODULE_SHI is used for the SPI master interface pins, so don't
reconfigure those. Instead manually configure the SHI pins using the
appropriate DEVALT bit.

BUG=chrome-os-partner:54328
BRANCH=None
TEST=Manual on kevin. Verify SHI continues to function on cold boot,
sysjump and resume from S3. Verify SPI sensors now function on resume
from S3 - `accelinit 0` succeeds.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180
Reviewed-on: https://chromium-review.googlesource.com/362061
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
4 years agoservo_micro: support servo micro v2, console gpio
Nick Sanders [Mon, 18 Jul 2016 19:59:13 +0000 (12:59 -0700)]
servo_micro: support servo micro v2, console gpio

* Remove GPIO USB endpoint to make room for update endpoint.
* Change GPIO mapping slightly to support servo micro v2.

BUG=chromium:571477
BRANCH=None
TEST=run servod, see new controls.

Change-Id: Id3b85b4c77b8f21afd9636b2ee459ace6f42f68e
Reviewed-on: https://chromium-review.googlesource.com/361383
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
4 years agokevin / gru: Enable low-power idle
Shawn Nematbakhsh [Wed, 22 Jun 2016 21:21:08 +0000 (14:21 -0700)]
kevin / gru: Enable low-power idle

BUG=chrome-os-partner:54343
BRANCH=None
TEST=Verify system continues to function as normal in S0 and S5.

Change-Id: I1b46c47a074a308f2e316e93813559d170bfe5ee
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355161
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>