sound: Use the general GpioOps paramater for max98357a
[depthcharge.git] / src / board / kunimitsu / board.c
1 /*
2  * Copyright (C) 2015 Google Inc.
3  * Copyright (C) 2015 Intel Corporation
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but without any warranty; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <gbb_header.h>
20 #include <pci.h>
21 #include <pci/pci.h>
22 #include <libpayload.h>
23 #include <sysinfo.h>
24
25 #include "base/init_funcs.h"
26 #include "base/list.h"
27 #include "drivers/bus/i2c/designware.h"
28 #include "drivers/bus/i2c/i2c.h"
29 #include "drivers/ec/cros/lpc.h"
30 #include "drivers/flash/flash.h"
31 #include "drivers/flash/memmapped.h"
32 #include "drivers/gpio/skylake.h"
33 #include "drivers/gpio/sysinfo.h"
34 #include "drivers/power/pch.h"
35 #include "drivers/sound/gpio_i2s.h"
36 #include "drivers/sound/gpio_pdm.h"
37 #include "drivers/sound/max98357a.h"
38 #include "drivers/sound/route.h"
39 #include "drivers/sound/ssm4567.h"
40 #include "drivers/storage/blockdev.h"
41 #include "drivers/storage/sdhci.h"
42 #include "drivers/tpm/lpc.h"
43 #include "drivers/tpm/tpm.h"
44 #include "vboot/util/flag.h"
45 #include "vboot/util/commonparams.h"
46 #include "drivers/bus/usb/usb.h"
47
48 /*
49  * Clock frequencies for the eMMC and SD ports are defined below. The minimum
50  * frequency is the same for both interfaces, the firmware does not run any
51  * interface faster than 52 MHz, but defines maximum eMMC frequency as 200 MHz
52  * for proper divider settings.
53  */
54 #define EMMC_SD_CLOCK_MIN       400000
55 #define EMMC_CLOCK_MAX          200000000
56 #define SD_CLOCK_MAX            52000000
57
58 /*
59  * Workaround for issue where silego is unable to see EC reset to clear the
60  * EC_IN_RW state when attempting to enter recovery via servo.  This allows FAFT
61  * to transition the system to developer mode.
62  */
63 static int ec_in_rw_workaround_get_value(GpioOps *me)
64 {
65         GoogleBinaryBlockHeader *gbb = cparams.gbb_data;
66
67         if (gbb->flags & GBB_FLAG_FAFT_KEY_OVERIDE) {
68                 /* Override is enabled, return 0 for FAFT. */
69                 printf("FAFT override enabled, returning 0 for ECINRW flag\n");
70                 return 0;
71         }
72
73         /* Override is not enabled, lookup the real GPIO state. */
74         GpioOps *ecinrw = sysinfo_lookup_gpio("EC in RW", 1,
75                             new_skylake_gpio_input_from_coreboot);
76         return ecinrw->get(ecinrw);
77 }
78
79 GpioOps *ec_in_rw_workaround_gpio(void)
80 {
81         GpioOps *ops = xzalloc(sizeof(*ops));
82
83         ops->get = &ec_in_rw_workaround_get_value;
84         return ops;
85 }
86
87 static int board_setup(void)
88 {
89         sysinfo_install_flags(new_skylake_gpio_input_from_coreboot);
90         flag_replace(FLAG_ECINRW, ec_in_rw_workaround_gpio());
91
92         /* MEC1322 Chrome EC */
93         CrosEcLpcBus *cros_ec_lpc_bus =
94                 new_cros_ec_lpc_bus(CROS_EC_LPC_BUS_MEC);
95         CrosEc *cros_ec = new_cros_ec(&cros_ec_lpc_bus->ops, 0, NULL);
96         CrosEc *cros_pd = new_cros_ec(&cros_ec_lpc_bus->ops, 1, NULL);
97         register_vboot_ec(&cros_ec->vboot, 0);
98         register_vboot_ec(&cros_pd->vboot, 1);
99
100         /* 16MB SPI Flash */
101         flash_set_ops(&new_mem_mapped_flash(0xff000000, 0x1000000)->ops);
102
103         /* SPI TPM memory mapped to act like LPC TPM */
104         tpm_set_ops(&new_lpc_tpm((void *)(uintptr_t)0xfed40000)->ops);
105
106         /* PCH Power */
107         power_set_ops(&skylake_power_ops);
108
109         /* eMMC */
110         SdhciHost *emmc = new_pci_sdhci_host(PCI_DEV(0, 0x1e, 4),
111                         SDHCI_PLATFORM_NO_EMMC_HS200,
112                         EMMC_SD_CLOCK_MIN, EMMC_CLOCK_MAX);
113         list_insert_after(&emmc->mmc_ctrlr.ctrlr.list_node,
114                         &fixed_block_dev_controllers);
115
116         /* SD Card */
117         SdhciHost *sd = new_pci_sdhci_host(PCI_DEV(0, 0x1e, 6), 1,
118                         EMMC_SD_CLOCK_MIN, SD_CLOCK_MAX);
119         list_insert_after(&sd->mmc_ctrlr.ctrlr.list_node,
120                         &removable_block_dev_controllers);
121
122         /* GPIO to activate buffer to isolate I2S from PCH & allow GPIO */
123         GpioCfg *boot_beep_gpio_cfg = new_skylake_gpio_output(GPP_F23, 0);
124
125         gpio_set(&boot_beep_gpio_cfg->ops, 1);
126
127         /* Use GPIO to bit-bang I2S to the codec */
128         GpioCfg *i2s2_bclk = new_skylake_gpio_output(GPP_F0, 0);
129         GpioCfg *i2s2_sfrm = new_skylake_gpio_output(GPP_F1, 0);
130         GpioCfg *i2s2_txd  = new_skylake_gpio_output(GPP_F2, 0);
131
132         /* Identify the codec on the daughter board */
133         GpioCfg *audio_db_id = new_skylake_gpio_input(GPP_E3);
134
135         if (gpio_get(&audio_db_id->ops)) {
136                 /* Speaker Amp Codec is on I2C4 */
137                 DesignwareI2c *i2c4 =
138                         new_pci_designware_i2c(PCI_DEV(0, 0x19, 2), 400000);
139                 ssm4567Codec *speaker_amp_left =
140                         new_ssm4567_codec(&i2c4->ops, 0x34, SSM4567_MODE_PDM);
141
142                 GpioPdm *pdm = new_gpio_pdm(
143                                 &i2s2_bclk->ops,        /* PDM Clock GPIO */
144                                 &i2s2_txd->ops,         /* PDM Data GPIO */
145                                 85000,                  /* Clock Start */
146                                 16000,                  /* Sample Rate */
147                                 2,                      /* Channels */
148                                 1000);                  /* Volume */
149
150                 SoundRoute *sound = new_sound_route(&pdm->ops);
151
152                 list_insert_after(&speaker_amp_left->component.list_node,
153                                 &sound->components);
154                 sound_set_ops(&sound->ops);
155         } else {
156                 /* Speaker Amp codec MAX98357A */
157                 GpioOps *sdmode_gpio = &new_skylake_gpio_output(GPP_E3, 0)->ops;
158                 max98357aCodec *speaker_amp =
159                         new_max98357a_codec(sdmode_gpio);
160
161                 GpioI2s *i2s = new_gpio_i2s(
162                                 &i2s2_bclk->ops,    /* I2S Bit Clock GPIO */
163                                 &i2s2_sfrm->ops,    /* I2S Frame Sync GPIO */
164                                 &i2s2_txd->ops,     /* I2S Data GPIO */
165                                 16000,              /* Sample rate */
166                                 2,                  /* Channels */
167                                 0x1FFF);            /* Volume */
168
169                 /* Connect the Codec to the I2S source */
170                 SoundRoute *sound = new_sound_route(&i2s->ops);
171
172                 list_insert_after(&speaker_amp->component.list_node,
173                                 &sound->components);
174                 sound_set_ops(&sound->ops);
175         }
176
177         return 0;
178 }
179
180 INIT_FUNC(board_setup);