Gale driver: Reduce the delay in I2C.
[depthcharge.git] / src / drivers / bus / i2c / ipq40xx_qup.c
1 /*
2  * This file is part of the depthcharge project.
3  *
4  * Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met:
9  *     * Redistributions of source code must retain the above copyright
10  *       notice, this list of conditions and the following disclaimer.
11  *     * Redistributions in binary form must reproduce the above
12  *       copyright notice, this list of conditions and the following
13  *       disclaimer in the documentation and/or other materials provided
14  *       with the distribution.
15  *     * Neither the name of The Linux Foundation nor the names of its
16  *       contributors may be used to endorse or promote products derived
17  *       from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
26  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
28  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
29  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include <arch/io.h>
33 #include <libpayload.h>
34 #include <base/container_of.h>
35 #include "drivers/bus/spi/ipq40xx.h"
36 #include "ipq40xx_qup.h"
37 #include "ipq40xx_blsp.h"
38
39 #define TIMEOUT_CNT     100
40
41 #define QUP_ADDR(id, reg)       (blsp_qup_base(id) + (reg))
42
43 #define QUP_DEBUG       0
44
45 #define QUPDBG          "\t-> "
46
47 #if QUP_DEBUG
48 #define qup_write32(a, v) do {                          \
49         write32(a, v);                                  \
50         printf(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n",  \
51                         __func__, __LINE__, a, v);      \
52 } while (0)
53 #else
54 #define qup_write32     write32
55 #endif
56
57 static qup_return_t qup_i2c_master_status(blsp_qup_id_t id)
58 {
59         uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS));
60
61         if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS)))
62                 return QUP_ERR_XFER_FAIL;
63
64 #if QUP_DEBUG
65         printf(QUPDBG "%s: 0x%x\n", __func__, reg_val);
66 #endif
67
68         if (reg_val & QUP_I2C_INVALID_READ_ADDR)
69                 return QUP_ERR_I2C_INVALID_SLAVE_ADDR;
70         if (reg_val & QUP_I2C_FAILED_MASK)
71                 return QUP_ERR_I2C_FAILED;
72         if (reg_val & QUP_I2C_ARB_LOST)
73                 return QUP_ERR_I2C_ARB_LOST;
74         if (reg_val & QUP_I2C_BUS_ERROR)
75                 return QUP_ERR_I2C_BUS_ERROR;
76         if (reg_val & QUP_I2C_INVALID_WRITE)
77                 return QUP_ERR_I2C_INVALID_WRITE;
78         if (reg_val & QUP_I2C_PACKET_NACK)
79                 return QUP_ERR_I2C_NACK;
80         if (reg_val & QUP_I2C_INVALID_TAG)
81                 return QUP_ERR_I2C_INVALID_TAG;
82
83         return QUP_SUCCESS;
84 }
85
86 static int check_bit_state(uint32_t *reg, int wait_for)
87 {
88         unsigned int count = TIMEOUT_CNT;
89
90         while ((read32(reg) &
91                 (BLSP_QUP_STATE_VALID_MASK | BLSP_QUP_STATE_MASK)) !=
92                         (BLSP_QUP_STATE_VALID | wait_for)) {
93                 if (count == 0)
94                         return QUP_ERR_TIMEOUT;
95                 count--;
96         }
97
98         return QUP_SUCCESS;
99 }
100
101 /*
102  * Check whether GSBIn_QUP State is valid
103  */
104 static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned wait_for)
105 {
106         return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for);
107 }
108
109 qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id)
110 {
111         /*
112          * The I2C_STATUS is a status register.
113          * Writing any value clears the status bits.
114          */
115         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0);
116         return QUP_SUCCESS;
117 }
118
119 static qup_return_t qup_reset_master_status(blsp_qup_id_t id)
120 {
121         qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C);
122         qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C);
123         qup_reset_i2c_master_status(id);
124         return QUP_SUCCESS;
125 }
126
127 static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status)
128 {
129         qup_return_t ret = QUP_ERR_UNDEFINED;
130         unsigned int count = TIMEOUT_CNT;
131
132         while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) {
133                 ret = qup_i2c_master_status(id);
134                 if (ret)
135                         return ret;
136                 if (count == 0)
137                         return QUP_ERR_TIMEOUT;
138                 count--;
139         }
140
141         return QUP_SUCCESS;
142 }
143
144 static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status)
145 {
146         qup_return_t ret = QUP_ERR_UNDEFINED;
147         unsigned int count = TIMEOUT_CNT;
148
149         while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) {
150                 ret = qup_i2c_master_status(id);
151                 if (ret)
152                         return ret;
153                 if (count == 0)
154                         return QUP_ERR_TIMEOUT;
155                 count--;
156         }
157
158         return QUP_SUCCESS;
159 }
160
161 static inline uint32_t qup_i2c_create_tag(int stop, u8 data)
162 {
163         uint32_t tag;
164
165         if (stop)
166                 tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data);
167         else
168                 tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data);
169
170         return tag;
171 }
172
173 static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id)
174 {
175         qup_return_t ret = QUP_ERR_UNDEFINED;
176
177         qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG);
178
179         mdelay(3);      /* TPM seems to need this */
180
181         ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY);
182         if (ret)
183                 return ret;
184
185         ret = qup_i2c_master_status(id);
186
187         if (ret)
188                 printf(QUPDBG "%s: error 0x%x\n", __func__, ret);
189
190         return ret;
191 }
192
193 static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
194                                        uint8_t stop_seq)
195 {
196         qup_return_t ret = QUP_ERR_UNDEFINED;
197                 uint8_t addr = p_tx_obj->p.iic.addr;
198                 uint8_t *data_ptr = p_tx_obj->p.iic.data;
199                 unsigned data_len = p_tx_obj->p.iic.data_len;
200                 unsigned idx = 0;
201         uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
202
203         qup_reset_master_status(id);
204
205         qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1);
206
207         qup_set_state(id, BLSP_QUP_STATE_RUN);
208
209         /*
210          * Since UNPACK enable is set in io mode register, populate 2 tags
211          * for each fifo register.
212          *
213          * Create the first tag as follows, with the start tag and first byte
214          * of the data to be written
215          *      +--------+--------+--------+--------+
216          *      | STOP / |  data  | START  | ADDR   |
217          *      |DATA tag|  byte  |  tag   | << 1   |
218          *      +--------+--------+--------+--------+
219          * rest will be created in the following while loop.
220          */
221         tag = qup_i2c_create_tag(data_len == 1 && stop_seq, data_ptr[idx]);
222         tag = ((tag << 16) & 0xffff0000) |
223                         (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr));
224         data_len--;
225         idx++;
226
227         qup_write32(fifo, tag);
228
229         while (data_len) {
230
231                 tag = qup_i2c_create_tag(data_len == 1 && stop_seq,
232                                 data_ptr[idx]);
233                 data_len--;
234                 idx++;
235
236                 if (data_len) {
237                         tag |= qup_i2c_create_tag(data_len == 1 && stop_seq,
238                                         data_ptr[idx]) << 16;
239                         data_len--;
240                         idx++;
241                 }
242
243                 qup_write32(fifo, tag);
244
245                 ret = qup_i2c_write_fifo_flush(id);
246
247                 if (ret) {
248                         printf(QUPDBG "%s: error\n", __func__);
249                         return ret;
250                 }
251         }
252
253         ret = qup_i2c_write_fifo_flush(id);
254
255         qup_set_state(id, BLSP_QUP_STATE_RESET);
256
257         return ret;
258 }
259
260 static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode,
261                                   qup_data_t *p_tx_obj, uint8_t stop_seq)
262 {
263         qup_return_t ret = QUP_ERR_UNDEFINED;
264
265         switch (mode) {
266         case QUP_MODE_FIFO:
267         case QUP_MODE_BLOCK:
268                 ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq);
269                 break;
270         default:
271                 ret = QUP_ERR_UNSUPPORTED;
272         }
273
274         if (ret) {
275                 qup_set_state(id, BLSP_QUP_STATE_RESET);
276                 printf(QUPDBG "%s() failed (%d)\n", __func__, ret);
277         }
278
279         return ret;
280 }
281
282 static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len)
283 {
284         int i, idx = 0;
285         int max = (len > 2) ? 2 : len;
286
287         for (i = 0; i < max; i++) {
288                 switch (QUP_I2C_MI_TAG(data)) {
289                 case QUP_I2C_MIDATA_SEQ:
290                         data_ptr[idx] = QUP_I2C_DATA(data);
291                         idx++;
292                         break;
293                 case QUP_I2C_MISTOP_SEQ:
294                         data_ptr[idx] = QUP_I2C_DATA(data);
295                         idx++;
296                         return idx;
297                 default:
298                         return -1;
299                 }
300
301                 data = (data >> 16);
302         }
303
304         return idx;
305 }
306
307 static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj)
308 {
309         qup_return_t ret = QUP_ERR_UNDEFINED;
310         uint8_t addr = p_tx_obj->p.iic.addr;
311         uint8_t *data_ptr = p_tx_obj->p.iic.data;
312         unsigned data_len = p_tx_obj->p.iic.data_len;
313         unsigned idx = 0;
314         uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
315
316         qup_reset_master_status(id);
317
318         qup_write32(QUP_ADDR(id, QUP_IO_MODES),
319                 QUP_UNPACK_EN | QUP_PACK_EN |
320                           ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
321                                         QUP_OUTPUT_MODE_SHFT) |
322                           ((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
323                                         QUP_INPUT_MODE_SHFT));
324
325         qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len);
326
327         qup_set_state(id, BLSP_QUP_STATE_RUN);
328
329         qup_write32(fifo, (QUP_I2C_START_SEQ |
330                                   (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) |
331                                 ((QUP_I2C_RECV_SEQ | data_len) << 16));
332
333         ret = qup_i2c_write_fifo_flush(id);
334         if (ret) {
335                 printf(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__);
336                 return ret;
337         }
338
339         ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG);
340         if (ret) {
341                 printf(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__);
342                 return ret;
343         }
344
345         fifo = QUP_ADDR(id, QUP_INPUT_FIFO);
346
347         while (data_len) {
348                 uint32_t data;
349                 int count;
350
351                 data = read32(fifo);
352                 mdelay(1);
353
354                 count = qup_i2c_parse_tag(data, data_ptr + idx, data_len);
355
356                 if (count < 0) {
357                         printf(QUPDBG "%s: Cannot parse tag 0x%x\n",
358                                         __func__, data);
359                         qup_set_state(id, BLSP_QUP_STATE_PAUSE);
360
361                         return QUP_ERR_I2C_INVALID_TAG;
362                 }
363
364                 idx += count;
365                 data_len -= count;
366
367                 qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG);
368         }
369
370         p_tx_obj->p.iic.data_len = idx;
371
372         qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0);
373
374         qup_set_state(id, BLSP_QUP_STATE_RESET);
375
376         return QUP_SUCCESS;
377 }
378
379 static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode,
380                                  qup_data_t *p_tx_obj)
381 {
382         qup_return_t ret = QUP_ERR_UNDEFINED;
383
384         qup_set_state(id, BLSP_QUP_STATE_RESET);
385
386         switch (mode) {
387         case QUP_MODE_FIFO:
388         case QUP_MODE_BLOCK:
389                 ret = qup_i2c_read_fifo(id, p_tx_obj);
390                 break;
391         default:
392                 ret = QUP_ERR_UNSUPPORTED;
393         }
394
395         if (ret) {
396                 qup_set_state(id, BLSP_QUP_STATE_RESET);
397                 printf(QUPDBG "%s() failed (%d)\n", __func__, ret);
398         }
399
400         return ret;
401 }
402
403 qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr)
404 {
405         qup_return_t ret = QUP_ERR_UNDEFINED;
406         uint32_t reg_val;
407
408         /* Reset the QUP core.*/
409         qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1);
410
411         /*Wait till the reset takes effect */
412         ret = qup_wait_for_state(id, BLSP_QUP_STATE_RESET);
413         if (ret)
414                 goto bailout;
415
416         /* Reset the config */
417         qup_write32(QUP_ADDR(id, QUP_CONFIG), 0);
418
419         /*Program the config register*/
420         /*Set N value*/
421         reg_val = 0x0F;
422         /*Set protocol*/
423         switch (config_ptr->protocol) {
424         case QUP_MINICORE_I2C_MASTER:
425                 reg_val |= ((config_ptr->protocol &
426                                 QUP_MINI_CORE_PROTO_MASK) <<
427                                 QUP_MINI_CORE_PROTO_SHFT);
428                 break;
429         default:
430                 ret = QUP_ERR_UNSUPPORTED;
431                 goto bailout;
432         }
433         reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN;
434         qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val);
435
436         /* Choose version 1 tag */
437         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0);
438
439         /* Reset i2c clk cntl register */
440         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0);
441
442         /* Set QUP IO Mode */
443         switch (config_ptr->mode) {
444         case QUP_MODE_FIFO:
445         case QUP_MODE_BLOCK:
446                 reg_val = QUP_UNPACK_EN | QUP_PACK_EN |
447                           ((config_ptr->mode & QUP_MODE_MASK) <<
448                                         QUP_OUTPUT_MODE_SHFT) |
449                           ((config_ptr->mode & QUP_MODE_MASK) <<
450                                         QUP_INPUT_MODE_SHFT);
451                 break;
452         default:
453                 ret = QUP_ERR_UNSUPPORTED;
454                 goto bailout;
455         }
456         qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val);
457
458         /*Set i2c clk cntl*/
459         reg_val = (QUP_DIVIDER_MIN_VAL << QUP_HS_DIVIDER_SHFT);
460         reg_val |= ((((config_ptr->src_frequency / config_ptr->clk_frequency)
461                         / 2) - QUP_DIVIDER_MIN_VAL) &
462                                 QUP_FS_DIVIDER_MASK);
463         qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), reg_val);
464
465         qup_set_state(id, BLSP_QUP_STATE_RESET);
466 bailout:
467         if (ret)
468                 printf(QUPDBG "failed to init qup (%d)\n", ret);
469
470         return ret;
471 }
472
473 qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
474 {
475         qup_return_t ret = QUP_ERR_UNDEFINED;
476         unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE));
477
478         if ((state >= BLSP_QUP_STATE_RESET && state <= BLSP_QUP_STATE_PAUSE)
479                 && (curr_state & BLSP_QUP_STATE_VALID_MASK)) {
480                 /*
481                 * For PAUSE_STATE to RESET_STATE transition,
482                 * two writes of  10[binary]) are required for the
483                 * transition to complete.
484                 */
485                 if (BLSP_QUP_STATE_PAUSE == curr_state &&
486                                         BLSP_QUP_STATE_RESET == state) {
487                         qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
488                         qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
489                 } else {
490                         qup_write32(QUP_ADDR(id, QUP_STATE), state);
491                 }
492                 ret = qup_wait_for_state(id, state);
493         }
494
495         return ret;
496 }
497
498 static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
499                                       uint8_t stop_seq)
500 {
501         qup_return_t ret = QUP_ERR_UNDEFINED;
502         uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
503                         QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK;
504
505         ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq);
506         if (0) {
507                 int i;
508
509                 printf("i2c tx bus %d device %2.2x:", id, p_tx_obj->p.iic.addr);
510                 for (i = 0; i < p_tx_obj->p.iic.data_len; i++)
511                         printf(" %2.2x", p_tx_obj->p.iic.data[i]);
512                 printf("\n");
513         }
514
515         return ret;
516 }
517
518 qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
519                            uint8_t stop_seq)
520 {
521         qup_return_t ret = QUP_ERR_UNDEFINED;
522
523         if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
524                         QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
525                 switch (p_tx_obj->protocol) {
526                 case QUP_MINICORE_I2C_MASTER:
527                         ret = qup_i2c_send_data(id, p_tx_obj, stop_seq);
528                         break;
529                 default:
530                         ret = QUP_ERR_UNSUPPORTED;
531                 }
532         }
533
534         return ret;
535 }
536
537 static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
538 {
539         qup_return_t ret = QUP_ERR_UNDEFINED;
540         uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
541                         QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK;
542
543         ret = qup_i2c_read(id, mode, p_rx_obj);
544         if (0) {
545                 int i;
546
547                 printf("i2c rxed on bus %d device %2.2x:",
548                         id, p_rx_obj->p.iic.addr);
549                 for (i = 0; i < p_rx_obj->p.iic.data_len; i++)
550                         printf(" %2.2x", p_rx_obj->p.iic.data[i]);
551                 printf("\n");
552         }
553
554         return ret;
555 }
556
557 qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
558 {
559         qup_return_t ret = QUP_ERR_UNDEFINED;
560
561         if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
562                         QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
563                 switch (p_rx_obj->protocol) {
564                 case QUP_MINICORE_I2C_MASTER:
565                         ret = qup_i2c_recv_data(id, p_rx_obj);
566                         break;
567                 default:
568                         ret = QUP_ERR_UNSUPPORTED;
569                 }
570         }
571
572         return ret;
573 }