reef: Add support for EC SW Sync
authorFurquan Shaikh <furquan@google.com>
Fri, 10 Jun 2016 00:27:18 +0000 (17:27 -0700)
committerchrome-bot <chrome-bot@chromium.org>
Fri, 10 Jun 2016 07:18:00 +0000 (00:18 -0700)
BUG=chrome-os-partner:54245
BRANCH=None
TEST=Verified that EC SW Sync works

Change-Id: I6efba59df7300868ec8515ddceabaf016c323b54
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351347
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
board/reef/defconfig
src/board/reef/board.c

index 09aeef0..5d2c6f6 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_BOARD="reef"
 CONFIG_FMAP_OFFSET=0x00204000
 
 # Vboot
+CONFIG_EC_SOFTWARE_SYNC=y
 CONFIG_VIRTUAL_DEV_SWITCH=y
 
 CONFIG_CROSSYSTEM_ACPI=y
@@ -17,6 +18,7 @@ CONFIG_NV_STORAGE_CMOS=y
 CONFIG_KERNEL_ZIMAGE=y
 
 # Drivers
+CONFIG_DRIVER_EC_CROS=y
 CONFIG_DRIVER_EC_CROS_LPC=y
 CONFIG_DRIVER_FLASH_MEMMAPPED=y
 CONFIG_DRIVER_INPUT_PS2=y
index 1a08279..c058119 100644 (file)
 #include <sysinfo.h>
 
 #include "base/init_funcs.h"
-#include "drivers/gpio/sysinfo.h"
+#include "drivers/ec/cros/lpc.h"
 #include "drivers/flash/memmapped.h"
+#include "drivers/gpio/sysinfo.h"
+#include "drivers/tpm/lpc.h"
 #include "drivers/tpm/tpm.h"
 #include "drivers/power/pch.h"
-#include "drivers/tpm/lpc.h"
 #include "drivers/storage/sdhci.h"
 
 #define EMMC_SD_CLOCK_MIN       400000
@@ -58,6 +59,12 @@ static int board_setup(void)
 {
        sysinfo_install_flags(NULL);
 
+       /* EC */
+       CrosEcLpcBus *cros_ec_lpc_bus =
+               new_cros_ec_lpc_bus(CROS_EC_LPC_BUS_GENERIC);
+       CrosEc *cros_ec = new_cros_ec(&cros_ec_lpc_bus->ops, 0, NULL);
+       register_vboot_ec(&cros_ec->vboot, 0);
+
        /* W25Q128FV SPI Flash */
        flash_set_ops(&new_mem_mapped_flash(FLASH_MEM_MAP_BASE,
                                         FLASH_MEM_MAP_SIZE)->ops);