Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq master
authorTom Rini <trini@ti.com>
Wed, 25 Feb 2015 23:14:18 +0000 (18:14 -0500)
committerTom Rini <trini@ti.com>
Wed, 25 Feb 2015 23:14:18 +0000 (18:14 -0500)
139 files changed:
Kconfig
arch/arm/Kconfig
arch/arm/cpu/arm1176/Makefile
arch/arm/cpu/arm1176/bcm2835/Kconfig
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm1176/tnetv107x/Makefile [deleted file]
arch/arm/cpu/arm1176/tnetv107x/aemif.c [deleted file]
arch/arm/cpu/arm1176/tnetv107x/clock.c [deleted file]
arch/arm/cpu/arm1176/tnetv107x/init.c [deleted file]
arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S [deleted file]
arch/arm/cpu/arm1176/tnetv107x/mux.c [deleted file]
arch/arm/cpu/arm1176/tnetv107x/timer.c [deleted file]
arch/arm/cpu/arm920t/Makefile
arch/arm/cpu/arm920t/a320/Makefile [deleted file]
arch/arm/cpu/arm920t/a320/reset.S [deleted file]
arch/arm/cpu/arm920t/a320/timer.c [deleted file]
arch/arm/cpu/arm920t/ks8695/Makefile [deleted file]
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S [deleted file]
arch/arm/cpu/arm920t/ks8695/timer.c [deleted file]
arch/arm/cpu/arm926ejs/Makefile
arch/arm/cpu/arm926ejs/mb86r0x/Makefile [deleted file]
arch/arm/cpu/arm926ejs/mb86r0x/clock.c [deleted file]
arch/arm/cpu/arm926ejs/mb86r0x/reset.c [deleted file]
arch/arm/cpu/arm926ejs/mb86r0x/timer.c [deleted file]
arch/arm/cpu/arm926ejs/pantheon/Makefile [deleted file]
arch/arm/cpu/arm926ejs/pantheon/cpu.c [deleted file]
arch/arm/cpu/arm926ejs/pantheon/dram.c [deleted file]
arch/arm/cpu/arm926ejs/pantheon/timer.c [deleted file]
arch/arm/cpu/armv7/exynos/Kconfig
arch/arm/cpu/armv7/omap3/Kconfig
arch/arm/cpu/armv7/s5pc1xx/Kconfig
arch/arm/cpu/armv7/uniphier/Kconfig
arch/arm/include/asm/arch-a320/a320.h [deleted file]
arch/arm/include/asm/arch-ks8695/platform.h [deleted file]
arch/arm/include/asm/arch-mb86r0x/hardware.h [deleted file]
arch/arm/include/asm/arch-mb86r0x/mb86r0x.h [deleted file]
arch/arm/include/asm/arch-pantheon/config.h [deleted file]
arch/arm/include/asm/arch-pantheon/cpu.h [deleted file]
arch/arm/include/asm/arch-pantheon/gpio.h [deleted file]
arch/arm/include/asm/arch-pantheon/mfp.h [deleted file]
arch/arm/include/asm/arch-pantheon/pantheon.h [deleted file]
arch/arm/include/asm/arch-tnetv107x/clock.h [deleted file]
arch/arm/include/asm/arch-tnetv107x/hardware.h [deleted file]
arch/arm/include/asm/arch-tnetv107x/mux.h [deleted file]
arch/arm/lib/asm-offsets.c
arch/arm/mach-davinci/Kconfig
arch/arm/mach-tegra/Kconfig
board/Marvell/dkb/Kconfig [deleted file]
board/Marvell/dkb/MAINTAINERS [deleted file]
board/Marvell/dkb/Makefile [deleted file]
board/Marvell/dkb/dkb.c [deleted file]
board/cm4008/Kconfig [deleted file]
board/cm4008/MAINTAINERS [deleted file]
board/cm4008/Makefile [deleted file]
board/cm4008/cm4008.c [deleted file]
board/cm4008/config.mk [deleted file]
board/cm4008/flash.c [deleted file]
board/cm41xx/Kconfig [deleted file]
board/cm41xx/MAINTAINERS [deleted file]
board/cm41xx/Makefile [deleted file]
board/cm41xx/cm41xx.c [deleted file]
board/cm41xx/config.mk [deleted file]
board/cm41xx/flash.c [deleted file]
board/compulab/cm_t335/Kconfig
board/davinci/da8xxevm/Kconfig
board/davinci/da8xxevm/MAINTAINERS
board/davinci/da8xxevm/Makefile
board/davinci/da8xxevm/README.hawkboard [deleted file]
board/davinci/da8xxevm/hawkboard-ais-nand.cfg [deleted file]
board/davinci/da8xxevm/hawkboard.c [deleted file]
board/davinci/da8xxevm/u-boot-spl-hawk.lds [deleted file]
board/faraday/a320evb/Kconfig [deleted file]
board/faraday/a320evb/MAINTAINERS [deleted file]
board/faraday/a320evb/Makefile [deleted file]
board/faraday/a320evb/a320evb.c [deleted file]
board/faraday/a320evb/lowlevel_init.S [deleted file]
board/gumstix/pepper/Kconfig
board/isee/igep0033/Kconfig
board/phytec/pcm051/Kconfig
board/samsung/goni/Kconfig
board/samsung/smdkc100/Kconfig
board/silica/pengwyn/Kconfig
board/syteco/jadecpu/Kconfig [deleted file]
board/syteco/jadecpu/MAINTAINERS [deleted file]
board/syteco/jadecpu/Makefile [deleted file]
board/syteco/jadecpu/jadecpu.c [deleted file]
board/syteco/jadecpu/lowlevel_init.S [deleted file]
board/ti/am335x/Kconfig
board/ti/tnetv107xevm/Kconfig [deleted file]
board/ti/tnetv107xevm/MAINTAINERS [deleted file]
board/ti/tnetv107xevm/Makefile [deleted file]
board/ti/tnetv107xevm/config.mk [deleted file]
board/ti/tnetv107xevm/sdb_board.c [deleted file]
common/Kconfig
config.mk
configs/a320evb_defconfig [deleted file]
configs/cm4008_defconfig [deleted file]
configs/cm41xx_defconfig [deleted file]
configs/dkb_defconfig [deleted file]
configs/hawkboard_defconfig [deleted file]
configs/hawkboard_uart_defconfig [deleted file]
configs/jadecpu_defconfig [deleted file]
configs/ph1_ld4_defconfig
configs/ph1_pro4_defconfig
configs/ph1_sld8_defconfig
configs/tnetv107x_evm_defconfig [deleted file]
doc/README.kconfig
doc/README.scrapyard
drivers/core/Kconfig
drivers/mtd/nand/Kconfig
drivers/net/Makefile
drivers/net/ks8695eth.c [deleted file]
drivers/serial/Makefile
drivers/serial/serial.c
drivers/serial/serial_ks8695.c [deleted file]
drivers/video/Makefile
drivers/video/mb86r0xgdc.c [deleted file]
drivers/watchdog/Makefile
drivers/watchdog/tnetv107x_wdt.c [deleted file]
dts/Kconfig
include/config_uncmd_spl.h
include/configs/a320evb.h [deleted file]
include/configs/cm4008.h [deleted file]
include/configs/cm41xx.h [deleted file]
include/configs/dkb.h [deleted file]
include/configs/hawkboard.h [deleted file]
include/configs/imx31_phycore.h
include/configs/jadecpu.h [deleted file]
include/configs/mx31ads.h
include/configs/omap3_igep00x0.h
include/configs/tnetv107x_evm.h [deleted file]
include/configs/zmx25.h
include/netdev.h
include/serial.h
scripts/Makefile.autoconf
scripts/Makefile.build
scripts/Makefile.spl
scripts/Makefile.uncmd_spl [new file with mode: 0644]
scripts/multiconfig.sh

diff --git a/Kconfig b/Kconfig
index fb012cf..91a0618 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -8,15 +8,13 @@ config UBOOTVERSION
        string
        option env="UBOOTVERSION"
 
-config KCONFIG_OBJDIR
-       string
-       option env="KCONFIG_OBJDIR"
+# Allow defaults in arch-specific code to override any given here
+source "arch/Kconfig"
 
 menu "General setup"
 
 config LOCALVERSION
        string "Local version - append to U-Boot release"
-       depends on !SPL_BUILD
        help
          Append an extra string to the end of your U-Boot version.
          This will show up on your boot log, for example.
@@ -27,7 +25,6 @@ config LOCALVERSION
 
 config LOCALVERSION_AUTO
        bool "Automatically append version information to the version string"
-       depends on !SPL_BUILD
        default y
        help
          This will try to automatically determine if the current tree is a
@@ -48,7 +45,6 @@ config LOCALVERSION_AUTO
 
 config CC_OPTIMIZE_FOR_SIZE
        bool "Optimize for size"
-       depends on !SPL_BUILD
        default y
        help
          Enabling this option will pass "-Os" instead of "-O2" to gcc
@@ -87,16 +83,6 @@ endmenu              # General setup
 
 menu "Boot images"
 
-config SPL_BUILD
-       bool
-       depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
-       default y
-
-config TPL_BUILD
-       bool
-       depends on $KCONFIG_OBJDIR="tpl"
-       default y
-
 config SUPPORT_SPL
        bool
 
@@ -106,23 +92,19 @@ config SUPPORT_TPL
 config SPL
        bool
        depends on SUPPORT_SPL
-       prompt "Enable SPL" if !SPL_BUILD
-       default y if SPL_BUILD
+       prompt "Enable SPL"
        help
          If you want to build SPL as well as the normal image, say Y.
 
 config TPL
        bool
        depends on SPL && SUPPORT_TPL
-       prompt "Enable TPL" if !SPL_BUILD
-       default y if TPL_BUILD
-       default n
+       prompt "Enable TPL"
        help
          If you want to build TPL as well as the normal image and SPL, say Y.
 
 config FIT
        bool "Support Flattened Image Tree"
-       depends on !SPL_BUILD
        help
          This option allows to boot the new uImage structrure,
          Flattened Image Tree.  FIT is formally a FDT, which can include
@@ -148,7 +130,6 @@ config FIT_SIGNATURE
 
 config SYS_EXTRA_OPTIONS
        string "Extra Options (DEPRECATED)"
-       depends on !SPL_BUILD
        help
          The old configuration infrastructure (= mkconfig + boards.cfg)
          provided the extra options field. If you have something like
@@ -174,8 +155,6 @@ config SYS_CLK_FREQ
 
 endmenu                # Boot images
 
-source "arch/Kconfig"
-
 source "common/Kconfig"
 
 source "dts/Kconfig"
index 820ba1c..7a2f91c 100644 (file)
@@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T
        bool "Support integratorcp_cm920t"
        select CPU_ARM920T
 
-config TARGET_A320EVB
-       bool "Support a320evb"
-       select CPU_ARM920T
-
 config ARCH_AT91
        bool "Atmel AT91"
 
@@ -88,14 +84,6 @@ config TARGET_SCB9328
        bool "Support scb9328"
        select CPU_ARM920T
 
-config TARGET_CM4008
-       bool "Support cm4008"
-       select CPU_ARM920T
-
-config TARGET_CM41XX
-       bool "Support cm41xx"
-       select CPU_ARM920T
-
 config TARGET_VCMA9
        bool "Support VCMA9"
        select CPU_ARM920T
@@ -144,10 +132,6 @@ config TARGET_DEVKIT3250
        bool "Support devkit3250"
        select CPU_ARM926EJS
 
-config TARGET_JADECPU
-       bool "Support jadecpu"
-       select CPU_ARM926EJS
-
 config TARGET_MX25PDK
        bool "Support mx25pdk"
        select CPU_ARM926EJS
@@ -227,10 +211,6 @@ config ORION5X
        bool "Marvell Orion"
        select CPU_ARM926EJS
 
-config TARGET_DKB
-       bool "Support dkb"
-       select CPU_ARM926EJS
-
 config TARGET_SPEAR300
        bool "Support spear300"
        select CPU_ARM926EJS
@@ -314,10 +294,6 @@ config TARGET_RPI_2
        bool "Support rpi_2"
        select CPU_V7
 
-config TARGET_TNETV107X_EVM
-       bool "Support tnetv107x_evm"
-       select CPU_ARM1176
-
 config TARGET_INTEGRATORAP_CM946ES
        bool "Support integratorap_cm946es"
        select CPU_ARM946ES
@@ -620,9 +596,8 @@ config TEGRA
        bool "NVIDIA Tegra"
        select SUPPORT_SPL
        select SPL
-       select OF_CONTROL if !SPL_BUILD
-       select CPU_ARM720T if SPL_BUILD
-       select CPU_V7 if !SPL_BUILD
+       select OF_CONTROL
+       select CPU_V7
 
 config TARGET_VEXPRESS64_AEMV8A
        bool "Support vexpress_aemv8a"
@@ -714,7 +689,7 @@ config ARCH_UNIPHIER
        select CPU_V7
        select SUPPORT_SPL
        select SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 endchoice
 
@@ -762,7 +737,6 @@ source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
@@ -779,8 +753,6 @@ source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
-source "board/cm4008/Kconfig"
-source "board/cm41xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
@@ -790,7 +762,6 @@ source "board/denx/m28evk/Kconfig"
 source "board/denx/m53evk/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
-source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
@@ -853,14 +824,12 @@ source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/sunxi/Kconfig"
-source "board/syteco/jadecpu/Kconfig"
 source "board/syteco/zmx25/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/ti/am43xx/Kconfig"
 source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
-source "board/ti/tnetv107xevm/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/tqc/tqma6/Kconfig"
index ead2303..480e130 100644 (file)
@@ -12,4 +12,3 @@ extra-y       = start.o
 obj-y  = cpu.o
 
 obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
index 162f973..73cc72b 100644 (file)
@@ -1,12 +1,12 @@
 if TARGET_RPI || TARGET_RPI_2
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 endif
index 0704bdd..ac937bf 100644 (file)
@@ -96,28 +96,6 @@ mmu_disable:
        mov     pc, r2
 mmu_disable_phys:
 
-#ifdef CONFIG_DISABLE_TCM
-       /*
-        * Disable the TCMs
-        */
-       mrc     p15, 0, r0, c0, c0, 2   /* Return TCM details */
-       cmp     r0, #0
-       beq     skip_tcmdisable
-       mov     r1, #0
-       mov     r2, #1
-       tst     r0, r2
-       mcrne   p15, 0, r1, c9, c1, 1   /* Disable Instruction TCM if present*/
-       tst     r0, r2, LSL #16
-       mcrne   p15, 0, r1, c9, c1, 0   /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
-       /* Peri port setup */
-       ldr     r0, =CONFIG_PERIPORT_BASE
-       orr     r0, r0, #CONFIG_PERIPORT_SIZE
-       mcr     p15,0,r0,c15,c2,4
 #endif
 
        /*
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644 (file)
index a4c1edf..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  += aemif.o clock.o init.o mux.o timer.o
-obj-y  += lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644 (file)
index a0f5728..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE                        TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs)          (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL     (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL                (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG    (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v)                ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v)          ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v)             (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v)            (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v)              (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v)             (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v)            (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v)              (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v)          (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v)                        (((v) & 0x03) << 0)
-
-#define NUM_CS                         4
-
-#define set_config_field(reg, field, val)                      \
-       do {                                                    \
-               if (val != -1) {                                \
-                       reg &= ~CONFIG_##field(0xffffffff);     \
-                       reg |=  CONFIG_##field(val);            \
-               }                                               \
-       } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
-       unsigned long tmp;
-
-       if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-               tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
-               tmp |= (1 << cs);
-               __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
-       } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-               tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
-               tmp |= (1 << cs);
-               __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
-       }
-
-       tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
-       set_config_field(tmp, SELECT_STROBE,    cfg->select_strobe);
-       set_config_field(tmp, EXTEND_WAIT,      cfg->extend_wait);
-       set_config_field(tmp, WR_SETUP,         cfg->wr_setup);
-       set_config_field(tmp, WR_STROBE,        cfg->wr_strobe);
-       set_config_field(tmp, WR_HOLD,          cfg->wr_hold);
-       set_config_field(tmp, RD_SETUP,         cfg->rd_setup);
-       set_config_field(tmp, RD_STROBE,        cfg->rd_strobe);
-       set_config_field(tmp, RD_HOLD,          cfg->rd_hold);
-       set_config_field(tmp, TURN_AROUND,      cfg->turn_around);
-       set_config_field(tmp, WIDTH,            cfg->width);
-
-       __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
-       int cs;
-
-       clk_enable(TNETV107X_LPSC_AEMIF);
-
-       for (cs = 0; cs < num_cs; cs++)
-               configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644 (file)
index 7ba28d3..0000000
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE             TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE               TNETV107X_PSC_BASE
-
-#define BIT(x)                 (1 << (x))
-
-#define MAX_PREDIV             64
-#define MAX_POSTDIV            8UL
-#define MAX_MULT               512
-#define MAX_DIV                        (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD              0x120
-#define PSC_PTSTAT             0x128
-#define PSC_MDSTAT(n)          (0x800 + (n) * 4)
-#define PSC_MDCTL(n)           (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ                BIT(8)
-
-#define psc_reg_read(reg)      __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val)        __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
-       u32     modes;
-       u32     postdiv;
-       u32     prediv;
-       u32     mult_factor;
-       u32     divider_range;
-       u32     bw_divider;
-       u32     spr_amount;
-       u32     spr_rate_div;
-       u32     diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
-       (struct sspll_regs *)(CLOCK_BASE + 0x040),
-       (struct sspll_regs *)(CLOCK_BASE + 0x080),
-       (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg)            (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg)       __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
-       u32     ctl;            /* 00 */
-       u32     ocsel;          /* 04 */
-       u32     secctl;         /* 08 */
-       u32     __pad0;
-       u32     mult;           /* 10 */
-       u32     prediv;         /* 14 */
-       u32     div1;           /* 18 */
-       u32     div2;           /* 1c */
-       u32     div3;           /* 20 */
-       u32     oscdiv1;        /* 24 */
-       u32     postdiv;        /* 28 */
-       u32     bpdiv;          /* 2c */
-       u32     wakeup;         /* 30 */
-       u32     __pad1;
-       u32     cmd;            /* 38 */
-       u32     stat;           /* 3c */
-       u32     alnctl;         /* 40 */
-       u32     dchange;        /* 44 */
-       u32     cken;           /* 48 */
-       u32     ckstat;         /* 4c */
-       u32     systat;         /* 50 */
-       u32     ckctl;          /* 54 */
-       u32     __pad2[2];
-       u32     div4;           /* 60 */
-       u32     div5;           /* 64 */
-       u32     div6;           /* 68 */
-       u32     div7;           /* 6c */
-       u32     div8;           /* 70 */
-};
-
-struct lpsc_map {
-       int     pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
-       (struct pllctl_regs *)(CLOCK_BASE + 0x700),
-       (struct pllctl_regs *)(CLOCK_BASE + 0x300),
-       (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg)           (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg)      __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val)        __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val)                    \
-       pllctl_reg_write(pll, reg,                              \
-               (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask)                     \
-       pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask)                     \
-       pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE         BIT(8)
-#define PLLCTL_PLLSELB         BIT(7)
-#define PLLCTL_PLLENSRC                BIT(5)
-#define PLLCTL_PLLDIS          BIT(4)
-#define PLLCTL_PLLRST          BIT(3)
-#define PLLCTL_PLLPWRDN                BIT(1)
-#define PLLCTL_PLLEN           BIT(0)
-
-#define PLLDIV_ENABLE          BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg)        offsetof(struct pllctl_regs, reg)
-       div_offset(div1), div_offset(div2), div_offset(div3),
-       div_offset(div4), div_offset(div5), div_offset(div6),
-       div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk                {SYS_PLL, 0}
-#define sys_dsp_clk            {SYS_PLL, 1}
-#define sys_ddr_clk            {SYS_PLL, 2}
-#define sys_full_clk           {SYS_PLL, 3}
-#define sys_lcd_clk            {SYS_PLL, 4}
-#define sys_vlynq_ref_clk      {SYS_PLL, 5}
-#define sys_tsc_clk            {SYS_PLL, 6}
-#define sys_half_clk           {SYS_PLL, 7}
-
-#define eth_clk_5              {ETH_PLL, 0}
-#define eth_clk_50             {ETH_PLL, 1}
-#define eth_clk_125            {ETH_PLL, 2}
-#define eth_clk_250            {ETH_PLL, 3}
-#define eth_clk_25             {ETH_PLL, 4}
-
-#define tdm_clk                        {TDM_PLL, 0}
-#define tdm_extra_clk          {TDM_PLL, 1}
-#define tdm1_clk               {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
-       [TNETV107X_LPSC_ARM]                    = sys_arm1176_clk,
-       [TNETV107X_LPSC_GEM]                    = sys_dsp_clk,
-       [TNETV107X_LPSC_DDR2_PHY]               = sys_ddr_clk,
-       [TNETV107X_LPSC_TPCC]                   = sys_full_clk,
-       [TNETV107X_LPSC_TPTC0]                  = sys_full_clk,
-       [TNETV107X_LPSC_TPTC1]                  = sys_full_clk,
-       [TNETV107X_LPSC_RAM]                    = sys_full_clk,
-       [TNETV107X_LPSC_MBX_LITE]               = sys_arm1176_clk,
-       [TNETV107X_LPSC_LCD]                    = sys_lcd_clk,
-       [TNETV107X_LPSC_ETHSS]                  = eth_clk_125,
-       [TNETV107X_LPSC_AEMIF]                  = sys_full_clk,
-       [TNETV107X_LPSC_CHIP_CFG]               = sys_half_clk,
-       [TNETV107X_LPSC_TSC]                    = sys_tsc_clk,
-       [TNETV107X_LPSC_ROM]                    = sys_half_clk,
-       [TNETV107X_LPSC_UART2]                  = sys_half_clk,
-       [TNETV107X_LPSC_PKTSEC]                 = sys_half_clk,
-       [TNETV107X_LPSC_SECCTL]                 = sys_half_clk,
-       [TNETV107X_LPSC_KEYMGR]                 = sys_half_clk,
-       [TNETV107X_LPSC_KEYPAD]                 = sys_half_clk,
-       [TNETV107X_LPSC_GPIO]                   = sys_half_clk,
-       [TNETV107X_LPSC_MDIO]                   = sys_half_clk,
-       [TNETV107X_LPSC_SDIO0]                  = sys_half_clk,
-       [TNETV107X_LPSC_UART0]                  = sys_half_clk,
-       [TNETV107X_LPSC_UART1]                  = sys_half_clk,
-       [TNETV107X_LPSC_TIMER0]                 = sys_half_clk,
-       [TNETV107X_LPSC_TIMER1]                 = sys_half_clk,
-       [TNETV107X_LPSC_WDT_ARM]                = sys_half_clk,
-       [TNETV107X_LPSC_WDT_DSP]                = sys_half_clk,
-       [TNETV107X_LPSC_SSP]                    = sys_half_clk,
-       [TNETV107X_LPSC_TDM0]                   = tdm_clk,
-       [TNETV107X_LPSC_VLYNQ]                  = sys_vlynq_ref_clk,
-       [TNETV107X_LPSC_MCDMA]                  = sys_half_clk,
-       [TNETV107X_LPSC_USB0]                   = sys_half_clk,
-       [TNETV107X_LPSC_TDM1]                   = tdm1_clk,
-       [TNETV107X_LPSC_DEBUGSS]                = sys_half_clk,
-       [TNETV107X_LPSC_ETHSS_RGMII]            = eth_clk_250,
-       [TNETV107X_LPSC_SYSTEM]                 = sys_half_clk,
-       [TNETV107X_LPSC_IMCOP]                  = sys_dsp_clk,
-       [TNETV107X_LPSC_SPARE]                  = sys_half_clk,
-       [TNETV107X_LPSC_SDIO1]                  = sys_half_clk,
-       [TNETV107X_LPSC_USB1]                   = sys_half_clk,
-       [TNETV107X_LPSC_USBSS]                  = sys_half_clk,
-       [TNETV107X_LPSC_DDR2_EMIF1_VRST]        = sys_ddr_clk,
-       [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]    = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
-       [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
-       [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
-       [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
-       unsigned long mult = 1, prediv = 1, postdiv = 1;
-       unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
-       unsigned long ret;
-       u32 bypass;
-
-       bypass = __raw_readl((u32 *)(CLOCK_BASE));
-       if (!(bypass & pll_bypass_mask[pll])) {
-               mult    = sspll_reg_read(pll, mult_factor);
-               prediv  = sspll_reg_read(pll, prediv) + 1;
-               postdiv = sspll_reg_read(pll, postdiv) + 1;
-       }
-
-       if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
-               ref = pll_ext_freq[pll];
-
-       if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
-               return ref;
-
-       ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
-       ret /= (prediv * postdiv);
-
-       return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
-                                       int div)
-{
-       int divider = 1;
-       unsigned long divreg;
-
-       divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
-       if (divreg & PLLDIV_ENABLE)
-               divider = (divreg & pll_div_mask[pll]) + 1;
-
-       return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
-       unsigned int fpll = pll_freq_get(pll);
-
-       return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
-                              unsigned long hz)
-{
-       int divider = (fpll / hz - 1);
-
-       divider &= pll_div_mask[pll];
-       divider |= PLLDIV_ENABLE;
-
-       __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
-       pllctl_reg_setbits(pll, alnctl, (1 << div));
-       pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
-       unsigned int fpll = pll_freq_get(pll);
-
-       __pll_div_freq_set(pll, fpll, div, hz);
-
-       pllctl_reg_write(pll, cmd, 1);
-
-       /* Wait until new divider takes effect */
-       while (pllctl_reg_read(pll, stat) & 0x01);
-
-       return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-       return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
-       unsigned long fpll, divider, pll;
-
-       pll = lpsc_clk_map[clk].pll;
-       fpll = pll_freq_get(pll);
-       divider = (fpll / hz - 1);
-       divider &= pll_div_mask[pll];
-
-       return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
-       unsigned long hz;
-
-       hz = clk_round_rate(clk, _hz);
-       if (hz != _hz)
-               return -EINVAL; /* Cannot set to target freq */
-
-       pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
-       return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
-       u32 mdctl;
-
-       mdctl = psc_reg_read(PSC_MDCTL(mod));
-       mdctl &= ~0x1f;
-       mdctl |= state;
-
-       if (lrstz == 0)
-               mdctl &= ~PSC_MDCTL_LRSTZ;
-       else if (lrstz == 1)
-               mdctl |= PSC_MDCTL_LRSTZ;
-
-       psc_reg_write(PSC_MDCTL(mod), mdctl);
-
-       psc_reg_write(PSC_PTCMD, 1);
-
-       /* wait for power domain transition to end */
-       while (psc_reg_read(PSC_PTSTAT) & 1);
-
-       /* Wait for module state change */
-       while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
-       return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
-       unsigned long fpll;
-       unsigned long best_pre = 0, best_post = 0, best_mult = 0;
-       unsigned long div, prediv, postdiv, mult;
-       unsigned long delta, actual;
-       long best_delta = -1;
-       int i;
-       u32 tmp;
-
-       if (data->pll == SYS_PLL)
-               return; /* cannot reconfigure system pll on the fly */
-
-       tmp = pllctl_reg_read(data->pll, ctl);
-       if (data->internal_osc) {
-               tmp &= ~PLLCTL_CLKMODE;
-               fpll = CONFIG_SYS_INT_OSC_FREQ;
-       } else {
-               tmp |= PLLCTL_CLKMODE;
-               fpll = pll_ext_freq[data->pll];
-       }
-       pllctl_reg_write(data->pll, ctl, tmp);
-
-       mult = data->pll_freq / fpll;
-       for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
-               div = (fpll * mult) / data->pll_freq;
-               if (div < 1 || div > MAX_DIV)
-                       continue;
-
-               for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
-                       prediv = div / postdiv;
-                       if (prediv < 1 || prediv > MAX_PREDIV)
-                               continue;
-
-                       actual = (fpll / prediv) * (mult / postdiv);
-                       delta = (actual - data->pll_freq);
-                       if (delta < 0)
-                               delta = -delta;
-                       if ((delta < best_delta) || (best_delta == -1)) {
-                               best_delta = delta;
-                               best_mult = mult;
-                               best_pre = prediv;
-                               best_post = postdiv;
-                               if (delta == 0)
-                                       goto done;
-                       }
-               }
-       }
-done:
-
-       if (best_delta == -1) {
-               printf("pll cannot derive %lu from %lu\n",
-                               data->pll_freq, fpll);
-               return;
-       }
-
-       fpll = fpll * best_mult;
-       fpll /= best_pre * best_post;
-
-       pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
-       pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
-       pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
-       pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-       pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
-       sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
-       sspll_reg_write(data->pll, prediv,      best_pre - 1);
-       sspll_reg_write(data->pll, postdiv,     best_post - 1);
-
-       for (i = 0; i < 10; i++)
-               if (data->div_freq[i])
-                       __pll_div_freq_set(data->pll, fpll, i,
-                                          data->div_freq[i]);
-
-       pllctl_reg_write(data->pll, cmd, 1);
-
-       /* Wait until pll "go" operation completes */
-       while (pllctl_reg_read(data->pll, stat) & 0x01);
-
-       pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-       pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
-       int i;
-
-       for (i = 0; i < num_pll; i++)
-               init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644 (file)
index d870826..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
-       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
-       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
-       icache_enable();
-       chip_configuration_unlock();
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644 (file)
index a8bce47..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
-       /* nothing for now, maybe needed for more exotic boot modes */
-       mov     pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644 (file)
index 310d84d..0000000
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1             0x00
-#define MUX_MODE_2             0x04
-#define MUX_MODE_3             0x0c
-#define MUX_MODE_4             0x1c
-
-#define MUX_DEBUG              0
-
-static const struct pin_config pin_table[] = {
-       /*                reg   shift   mode    */
-       TNETV107X_MUX_CFG(0,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(0,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(0,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(0,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(0,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(0,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(0,    25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(1,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(1,    25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(2,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(2,    25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(3,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(3,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    10,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(3,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(3,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    20,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(3,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(3,    25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(3,    25,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(4,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(4,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(4,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(4,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    20,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(4,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(4,    25,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    10,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    20,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(5,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(5,    25,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    10,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    20,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(6,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(6,    25,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(7,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(7,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(7,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    10,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(7,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(7,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(7,    25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(7,    25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(8,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(8,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(8,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(8,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(8,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(8,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(8,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(9,    0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    0,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(9,    5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(9,    5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    5,      MUX_MODE_4),
-       TNETV107X_MUX_CFG(9,    10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(9,    10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    10,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(9,    15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(9,    15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(9,    20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(9,    20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(9,    20,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(10,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(10,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(10,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(10,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(10,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(10,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(10,   25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(11,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(11,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(12,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(13,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(13,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(13,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(13,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(14,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(15,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(15,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(15,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(16,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(16,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(16,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(16,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(16,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(16,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(16,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(17,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(17,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(17,   0,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(17,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(17,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(17,   5,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(17,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(17,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(17,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(17,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(17,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(17,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(18,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(18,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(18,   0,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(18,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(18,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(18,   5,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(18,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(18,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(18,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(18,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(18,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(18,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(19,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(19,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(19,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(19,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(19,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(19,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(20,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(20,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(21,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   5,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(22,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(22,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(22,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(22,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   20,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(22,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(22,   25,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(23,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(23,   0,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(23,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(23,   5,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(23,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(23,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(24,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(24,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(24,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(24,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(24,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(24,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(24,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(24,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(24,   25,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(25,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(25,   0,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(25,   0,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(25,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(25,   5,      MUX_MODE_2),
-       TNETV107X_MUX_CFG(25,   5,      MUX_MODE_3),
-       TNETV107X_MUX_CFG(25,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(25,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(25,   10,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(25,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(25,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(25,   15,     MUX_MODE_3),
-       TNETV107X_MUX_CFG(25,   15,     MUX_MODE_4),
-       TNETV107X_MUX_CFG(26,   0,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   5,      MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   10,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   10,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(26,   15,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   15,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(26,   20,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   20,     MUX_MODE_2),
-       TNETV107X_MUX_CFG(26,   25,     MUX_MODE_1),
-       TNETV107X_MUX_CFG(26,   25,     MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
-       const struct pin_config *cfg;
-       unsigned long mask, mode, reg;
-
-       if (index >= pin_table_size)
-               return 0;
-
-       cfg = &pin_table[index];
-
-       mask = 0x1f << cfg->mask_offset;
-       mode = cfg->mode << cfg->mask_offset;
-
-       reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
-       reg = (reg & ~mask) | mode;
-       __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
-       return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
-       int i, ret = 1;
-
-       for (i = 0; pins[i] >= 0; i++)
-               ret &= mux_select_pin(pins[i]);
-
-       return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644 (file)
index 6e0dd0d..0000000
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
-       u_int32_t pid12;
-       u_int32_t pad[3];
-       u_int32_t tim12;
-       u_int32_t tim34;
-       u_int32_t prd12;
-       u_int32_t prd34;
-       u_int32_t tcr;
-       u_int32_t tgcr;
-       u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV    16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-       clk_enable(TNETV107X_LPSC_TIMER0);
-
-       lastinc = timestamp = 0;
-
-       /* We are using timer34 in unchained 32-bit mode, full speed */
-       __raw_writel(0x0, &regs->tcr);
-       __raw_writel(0x0, &regs->tgcr);
-       __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
-       __raw_writel(0x0, &regs->tim34);
-       __raw_writel(TIMER_LOAD_VAL, &regs->prd34);
-       __raw_writel(2 << 22, &regs->tcr);
-
-       return 0;
-}
-
-static ulong get_timer_raw(void)
-{
-       ulong now = __raw_readl(&regs->tim34);
-
-       if (now >= lastinc)
-               timestamp += now - lastinc;
-       else
-               timestamp += now + TIMER_LOAD_VAL - lastinc;
-
-       lastinc = now;
-
-       return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-       return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-       tmo *= usec;
-       tmo /= (1000 * TIM_CLK_DIV);
-
-       endtime = get_timer_raw() + tmo;
-
-       do {
-               ulong now = get_timer_raw();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
-       return CONFIG_SYS_HZ;
-}
index a16838b..6582938 100644 (file)
@@ -10,8 +10,6 @@ extra-y       = start.o
 obj-y  += cpu.o
 obj-$(CONFIG_USE_IRQ)  += interrupts.o
 
-obj-$(if $(filter a320,$(SOC)),y) += a320/
 obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
 obj-$(CONFIG_S3C24X0) += s3c24x0/
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644 (file)
index bbdab58..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  += reset.o
-obj-y  += timer.o
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644 (file)
index 81f9dc9..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
-       b       reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644 (file)
index 1ac5b60..0000000
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK    32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       tick *= CONFIG_SYS_HZ;
-       do_div(tick, gd->arch.timer_rate_hz);
-
-       return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-       usec *= gd->arch.timer_rate_hz;
-       do_div(usec, 1000000);
-
-       return usec;
-}
-
-int timer_init(void)
-{
-       struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-       unsigned int cr;
-
-       debug("%s()\n", __func__);
-
-       /* disable timers */
-       writel(0, &tmr->cr);
-
-       /* use 32768Hz oscillator for RTC, WDT, TIMER */
-       ftpmu010_32768osc_enable();
-
-       /* setup timer */
-       writel(TIMER_LOAD_VAL, &tmr->timer3_load);
-       writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
-       writel(0, &tmr->timer3_match1);
-       writel(0, &tmr->timer3_match2);
-
-       /* we don't want timer to issue interrupts */
-       writel(FTTMR010_TM3_MATCH1 |
-              FTTMR010_TM3_MATCH2 |
-              FTTMR010_TM3_OVERFLOW,
-              &tmr->interrupt_mask);
-
-       cr = readl(&tmr->cr);
-       cr |= FTTMR010_TM3_CLOCK;       /* use external clock */
-       cr |= FTTMR010_TM3_ENABLE;
-       writel(cr, &tmr->cr);
-
-       gd->arch.timer_rate_hz = TIMER_CLOCK;
-       gd->arch.tbu = gd->arch.tbl = 0;
-
-       return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-       struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-       ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
-       /* increment tbu if tbl has rolled over */
-       if (now < gd->arch.tbl)
-               gd->arch.tbu++;
-       gd->arch.tbl = now;
-       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
-       unsigned long long start;
-       ulong tmo;
-
-       start = get_ticks();            /* get current timestamp */
-       tmo = usec_to_tick(usec);       /* convert usecs to ticks */
-       while ((get_ticks() - start) < tmo)
-               ;                       /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
-       return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-       return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644 (file)
index 400aa89..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = lowlevel_init.o
-obj-y  += timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644 (file)
index a2a07f2..0000000
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
-       ldr     \reg0, =\cycles
-       subs    \reg0, \reg0, #1
-       subne   pc,  pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
-       /*
-        * enable UART for early debug trace
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-       mov     r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
-       str     r2, [r1]
-       ldr     r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-       mov     r2, #KS8695_UART_LINEC_WLEN8
-       str     r2, [r1]                /* 8 data bits, no parity, 1 stop */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
-       mov     r2, #0x41
-       str     r2, [r1]                /* write 'A' */
-#endif
-#if DEBUG
-       ldr     r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
-       mov     r2, #0x42
-       str     r2, [r1]
-#endif
-
-       /*
-        * remap the memory and flash regions. we want to end up with
-        * ram from address 0, and flash at 32MB.
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
-       ldr     r2, =0xbfc00040
-       str     r2, [r1]                /* large flash map */
-       ldr     pc, =(highflash+0x02000000-0x00f00000)  /* jump to high flash address */
-highflash:
-       ldr     r2, =0x8fe00040
-       str     r2, [r1]                /* remap flash range */
-
-       /*
-        * remap the second select region to the 4MB immediately after
-        * the first region. This way if you have a larger flash (say 8Mb)
-        * then you can have it all mapped nicely. Has no effect if you
-        * only have a 4Mb or smaller flash.
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
-       ldr     r2, =0x9fe40040
-       str     r2, [r1]                /* remap flash2 region, contiguous */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
-       ldr     r2, =0x30000005
-       str     r2, [r1]                /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
-       /*
-        * map the second flash chip, using the external IO lines.
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
-       ldr     r2, =0xafe80b6d
-       str     r2, [r1]                /* remap io0 region, contiguous */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
-       ldr     r2, =0xbfec0b6d
-       str     r2, [r1]                /* remap io1 region, contiguous */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
-       ldr     r2, =0x30050005
-       str     r2, [r1]                /* enable second flash */
-#endif
-
-       /*
-        * before relocating, we have to setup RAM timing
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-       ldr     r2, =0x7fc0000e         /* 32MB */
-#else
-       ldr     r2, =0x3fc0000e         /* 16MB */
-#endif
-       str     r2, [r1]                /* configure sdram bank0 setup */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
-       mov     r2, #0
-       str     r2, [r1]                /* configure sdram bank1 setup */
-
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
-       ldr     r2, =0x0000000a
-       str     r2, [r1]                /* set RAS/CAS timing */
-
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-       ldr     r2, =0x00030000
-       str     r2, [r1]                /* send NOP command */
-       DELAY_FOR 0x100, r0
-       ldr     r2, =0x00010000
-       str     r2, [r1]                /* send PRECHARGE-ALL */
-       DELAY_FOR 0x100, r0
-
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
-       ldr     r2, =0x00000020
-       str     r2, [r1]                /* set for fast refresh */
-       DELAY_FOR 0x100, r0
-       ldr     r2, =0x00000190
-       str     r2, [r1]                /* set normal refresh timing */
-
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-       ldr     r2, =0x00020033
-       str     r2, [r1]                /* send mode command */
-       DELAY_FOR 0x100, r0
-       ldr     r2, =0x01f00000
-       str     r2, [r1]                /* enable sdram fifos */
-
-       /*
-        * set pll to top speed
-        */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
-       mov     r2, #0
-       str     r2, [r1]                /* set pll clock to 166MHz */
-
-       ldr     r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
-       ldr     r2, [r1]                /* Get switch ctrl0 register       */
-       and     r2, r2, #0x0fc00000     /* Mask out LED control bits       */
-       orr     r2, r2, #0x01800000     /* Set Link/activity/speed actions */
-       str     r2, [r1]
-
-#ifdef CONFIG_CM4008
-       ldr     r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
-       ldr     r2, =0x0000fe30
-       str     r2, [r1]                /* enable LED's as outputs          */
-       ldr     r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
-       ldr     r2, =0x0000fe20
-       str     r2, [r1]                /* turn on power LED                */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
-       ldr     r2, [r1]                /* get current GPIO input data      */
-       tst     r2, #0x8                /* check if "erase" depressed       */
-       beq     nobutton
-       mov     r2, #0                  /* be quiet on boot, no console     */
-       ldr     r1, =serial_console
-       str     r2, [r1]
-nobutton:
-#endif
-
-       add     lr, lr, #0x02000000     /* flash is now mapped high */
-       add     ip, ip, #0x02000000     /* this is a hack */
-       mov     pc, lr                  /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644 (file)
index 23db557..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define        TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_1)
-#define        TIMER_COUNT     (TIMER_INTERVAL / 2)
-#define        TIMER_PULSE     TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define        ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define        ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
-       /* Set the hadware timer for 1ms */
-       ks8695_write(KS8695_TIMER1, TIMER_COUNT);
-       ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
-       ks8695_write(KS8695_TIMER_CTRL, 0x2);
-       timer_ticks = 0;
-
-       return 0;
-}
-
-ulong get_timer_masked(void)
-{
-       /* Check for timer wrap */
-       if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
-               /* Clear interrupt condition */
-               ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
-               timer_ticks++;
-       }
-       return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
-       return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
-       ulong start = get_timer_masked();
-       ulong end;
-
-       /* Only 1ms resolution :-( */
-       end = usec / 1000;
-       while (get_timer(start) < end)
-               ;
-}
-
-void reset_cpu (ulong ignored)
-{
-       ulong tc;
-
-       /* Set timer0 to watchdog, and let it timeout */
-       tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
-       ks8695_write(KS8695_TIMER_CTRL, tc);
-       ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
-       ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
-       /* Should only wait here till watchdog resets */
-       for (;;)
-               ;
-}
index f5944cc..63fa159 100644 (file)
@@ -16,9 +16,7 @@ endif
 
 obj-$(CONFIG_ARMADA100) += armada100/
 obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
 obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_PANTHEON) += pantheon/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644 (file)
index 365892c..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644 (file)
index 1f6f66e..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
-       struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
-                                       MB86R0x_CRG_BASE;
-       uint32_t pllmode;
-
-       pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
-       if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
-               return 40000000;
-
-       return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644 (file)
index 7bd77ff..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
-       struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
-                                       MB86R0x_CRG_BASE;
-
-       writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
-       while (1)
-               /* NOP */;
-       /* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644 (file)
index bb07819..0000000
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ     (CONFIG_MB86R0x_IOCLK  / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       tick *= CONFIG_SYS_HZ;
-       do_div(tick, TIMER_FREQ);
-
-       return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-       usec *= TIMER_FREQ;
-       do_div(usec, 1000000);
-
-       return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
-       struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
-                                       MB86R0x_TIMER_BASE;
-       ulong ctrl = readl(&timer->control);
-
-       writel(TIMER_LOAD_VAL, &timer->load);
-
-       ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
-               MB86R0x_TIMER_SIZE_32;
-
-       writel(ctrl, &timer->control);
-
-       /* capture current value time */
-       lastdec = readl(&timer->value);
-       timestamp = 0; /* start "advancing" time stamp from 0 */
-
-       return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
-       struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
-                                       MB86R0x_TIMER_BASE;
-       ulong now = readl(&timer->value);
-
-       if (now <= lastdec) {
-               /* normal mode (non roll) */
-               /* move stamp forward with absolut diff ticks */
-               timestamp += lastdec - now;
-       } else {
-               /* we have rollover of incrementer */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-       lastdec = now;
-       return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-       return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
-       unsigned long long tmp;
-       ulong tmo;
-
-       tmo = usec_to_tick(usec);
-       tmp = get_ticks();                      /* get current timestamp */
-
-       while ((get_ticks() - tmp) < tmo)       /* loop till event */
-                /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
-       return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-       ulong tbclk;
-
-       tbclk = TIMER_FREQ;
-       return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644 (file)
index 988341f..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644 (file)
index 4e2a177..0000000
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ        (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID    (1<<8)
-#define L2C_RAM_SEL    (1<<4)
-
-int arch_cpu_init(void)
-{
-       u32 val;
-       struct panthcpu_registers *cpuregs =
-               (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-       struct panthapb_registers *apbclkres =
-               (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
-       struct panthmpmu_registers *mpmu =
-               (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
-       struct panthapmu_registers *apmu =
-               (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
-       /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
-       val = readl(&cpuregs->cpu_conf);
-       val = val | SET_MRVL_ID;
-       writel(val, &cpuregs->cpu_conf);
-
-       /* Turn on clock gating (PMUM_CCGR) */
-       writel(0xFFFFFFFF, &mpmu->ccgr);
-
-       /* Turn on clock gating (PMUM_ACGR) */
-       writel(0xFFFFFFFF, &mpmu->acgr);
-
-       /* Turn on uart2 clock */
-       writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
-       /* Enable GPIO clock */
-       writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
-       /* Enable I2C clock */
-       writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-       writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
-       /* Enable mmc clock */
-       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
-                       &apmu->sd1);
-       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
-                       &apmu->sd3);
-#endif
-
-       icache_enable();
-
-       return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-       u32 id;
-       struct panthcpu_registers *cpuregs =
-               (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-       id = readl(&cpuregs->chip_id);
-       printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-       return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644 (file)
index f77e3d0..0000000
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
-       u32     cs;     /* Memory Address Map Register -CS */
-       u32     pad[3];
-};
-
-struct panthddr_registers {
-       u8      pad[0x100 - 0x000];
-       struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
-       struct panthddr_registers *ddr_regs =
-               (struct panthddr_registers *)PANTHEON_DRAM_BASE;
-       u32 result = 0;
-       u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-       if (!CS_valid)
-               return 0;
-
-       result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-       return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
-       struct panthddr_registers *ddr_regs =
-               (struct panthddr_registers *)PANTHEON_DRAM_BASE;
-       u32 result = 0;
-       u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-       if (!CS_valid)
-               return 0;
-
-       result = readl(&ddr_regs->mmap[chip_sel].cs);
-       result = (result >> 16) & 0xF;
-       if (result < 0x7) {
-               printf("Unknown DRAM Size\n");
-               return -1;
-       } else {
-               return ((0x8 << (result - 0x7)) * 1024 * 1024);
-       }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
-       int i;
-
-       gd->ram_size = 0;
-       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-               gd->bd->bi_dram[i].start = panth_sdram_base(i);
-               gd->bd->bi_dram[i].size = panth_sdram_size(i);
-               /*
-                * It is assumed that all memory banks are consecutive
-                * and without gaps.
-                * If the gap is found, ram_size will be reported for
-                * consecutive memory only
-                */
-               if (gd->bd->bi_dram[i].start != gd->ram_size)
-                       break;
-
-               gd->ram_size += gd->bd->bi_dram[i].size;
-
-       }
-
-       for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-               /*
-                * If above loop terminated prematurely, we need to set
-                * remaining banks' start address & size as 0. Otherwise other
-                * u-boot functions and Linux kernel gets wrong values which
-                * could result in crash
-                */
-               gd->bd->bi_dram[i].start = 0;
-               gd->bd->bi_dram[i].size = 0;
-       }
-       return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
-       dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644 (file)
index 6382d3b..0000000
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
-       u32 clk_ctrl;   /* Timer clk control reg */
-       u32 match[9];   /* Timer match registers */
-       u32 count[3];   /* Timer count registers */
-       u32 status[3];
-       u32 ie[3];
-       u32 preload[3]; /* Timer preload value */
-       u32 preload_ctrl[3];
-       u32 wdt_match_en;
-       u32 wdt_match_r;
-       u32 wdt_val;
-       u32 wdt_sts;
-       u32 icr[3];
-       u32 wdt_icr;
-       u32 cer;        /* Timer count enable reg */
-       u32 cmr;
-       u32 ilr[3];
-       u32 wcr;
-       u32 wfar;
-       u32 wsar;
-       u32 cvwr[3];
-};
-
-#define TIMER                  0       /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)           ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL                 0xffffffff
-#define        COUNT_RD_REQ            0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-       struct panthtmr_registers *panthtimers =
-               (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-       volatile int loop=100;
-       ulong val;
-
-       writel(COUNT_RD_REQ, &panthtimers->cvwr);
-       while (loop--)
-               val = readl(&panthtimers->cvwr);
-
-       /*
-        * This stop gcc complain and prevent loop mistake init to 0
-        */
-       val = readl(&panthtimers->cvwr);
-
-       return val;
-}
-
-ulong get_timer_masked(void)
-{
-       ulong now = read_timer();
-
-       if (now >= gd->arch.tbl) {
-               /* normal mode */
-               gd->arch.tbu += now - gd->arch.tbl;
-       } else {
-               /* we have an overflow ... */
-               gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
-       }
-       gd->arch.tbl = now;
-
-       return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
-       return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-               base);
-}
-
-void __udelay(unsigned long usec)
-{
-       ulong delayticks;
-       ulong endtime;
-
-       delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-       endtime = get_timer_masked() + delayticks;
-
-       while (get_timer_masked() < endtime)
-               ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-       struct panthapb_registers *apb1clkres =
-               (struct panthapb_registers *) PANTHEON_APBC_BASE;
-       struct panthtmr_registers *panthtimers =
-               (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
-       /* Enable Timer clock at 3.25 MHZ */
-       writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-       /* load value into timer */
-       writel(0x0, &panthtimers->clk_ctrl);
-       /* Use Timer 0 Match Resiger 0 */
-       writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
-       /* Preload value is 0 */
-       writel(0x0, &panthtimers->preload[TIMER]);
-       /* Enable match comparator 0 for Timer 0 */
-       writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
-       /* Enable timer 0 */
-       writel(0x1, &panthtimers->cer);
-       /* init the gd->arch.tbu and gd->arch.tbl value */
-       gd->arch.tbl = read_timer();
-       gd->arch.tbu = 0;
-
-       return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR       0xbaba  /* WDT Register First key */
-#define TMP_WSAR       0xeb10  /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
-       struct panthmpmu_registers *mpmu =
-               (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
-       struct panthtmr_registers *panthtimers =
-               (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
-       u32 val;
-
-       /* negate hardware reset to the WDT after system reset */
-       val = readl(&mpmu->aprr);
-       val = val | MPMU_APRR_WDTR;
-       writel(val, &mpmu->aprr);
-
-       /* reset/enable WDT clock */
-       writel(APBC_APBCLK, &mpmu->wdtpcr);
-
-       /* clear previous WDT status */
-       writel(TMR_WFAR, &panthtimers->wfar);
-       writel(TMP_WSAR, &panthtimers->wsar);
-       writel(0, &panthtimers->wdt_sts);
-
-       /* set match counter */
-       writel(TMR_WFAR, &panthtimers->wfar);
-       writel(TMP_WSAR, &panthtimers->wsar);
-       writel(0xf, &panthtimers->wdt_match_r);
-
-       /* enable WDT reset */
-       writel(TMR_WFAR, &panthtimers->wfar);
-       writel(TMP_WSAR, &panthtimers->wsar);
-       writel(0x3, &panthtimers->wdt_match_en);
-
-       /*enable functional WDT clock */
-       writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-       return (ulong)CONFIG_SYS_HZ;
-}
index 2064efa..eb86a7f 100644 (file)
@@ -6,7 +6,7 @@ choice
 config TARGET_SMDKV310
        select SUPPORT_SPL
        bool "Exynos4210 SMDKV310 board"
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_TRATS
        bool "Exynos4210 Trats board"
@@ -33,32 +33,32 @@ config TARGET_ARNDALE
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_SMDK5250
        bool "SMDK5250 board"
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_SNOW
        bool "Snow board"
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_SMDK5420
        bool "SMDK5420 board"
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_PEACH_PI
        bool "Peach Pi board"
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_PEACH_PIT
        bool "Peach Pit board"
        select SUPPORT_SPL
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 endchoice
 
@@ -66,25 +66,25 @@ config SYS_SOC
        default "exynos"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 config DM_SPI
-       default y if !SPL_BUILD
+       default y
 
 config DM_SPI_FLASH
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config SYS_MALLOC_F
-       default y if !SPL_BUILD
+       default y
 
 config SYS_MALLOC_F_LEN
-       default 0x400 if !SPL_BUILD
+       default 0x400
 
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
index 4644098..4a0ac2c 100644 (file)
@@ -94,19 +94,19 @@ config TARGET_TWISTER
 endchoice
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config DM_SERIAL
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config SYS_MALLOC_F
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config SYS_MALLOC_F_LEN
-       default 0x400 if DM && !SPL_BUILD
+       default 0x400 if DM
 
 config SYS_SOC
        default "omap3"
index 6288134..bc73813 100644 (file)
@@ -5,11 +5,11 @@ choice
 
 config TARGET_S5P_GONI
        bool "S5P Goni board"
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 config TARGET_SMDKC100
        bool "Support smdkc100 board"
-       select OF_CONTROL if !SPL_BUILD
+       select OF_CONTROL
 
 endchoice
 
index 1a47ac9..8335685 100644 (file)
@@ -52,7 +52,7 @@ config SYS_MALLOC_F
        default y
 
 config SYS_MALLOC_F_LEN
-       default 0x2000
+       default 0x400
 
 config CMD_PINMON
        bool "Enable boot mode pins monitor command"
@@ -64,14 +64,12 @@ config CMD_PINMON
 
 config CMD_DDRPHY_DUMP
        bool "Enable dump command of DDR PHY parameters"
-       depends on !SPL_BUILD
        help
          The command "ddrphy" shows the resulting parameters of DDR PHY
          training; it is useful for the evaluation of DDR PHY training.
 
 choice
        prompt "DDR3 Frequency select"
-       depends on SPL_BUILD
 
 config DDR_FREQ_1600
        bool "DDR3 1600"
diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h
deleted file mode 100644 (file)
index f2db8e1..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE   0x90200000      /* Static Memory Controller */
-#define CONFIG_DEBUG_LED       0x902ffffc      /* Debug LED */
-#define CONFIG_FTSDMC020_BASE  0x90300000      /* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE   0x90900000      /* Ethernet */
-#define CONFIG_FTPMU010_BASE   0x98100000      /* Power Management Unit */
-#define CONFIG_FTTMR010_BASE   0x98400000      /* Timer */
-#define CONFIG_FTRTC010_BASE   0x98600000      /* Real Time Clock*/
-
-#endif /* __A320_H */
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h
deleted file mode 100644 (file)
index 02f6049..0000000
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef __address_h
-#define __address_h                    1
-
-#define KS8695_SDRAM_START         0x00000000
-#define KS8695_SDRAM_SIZE          0x01000000
-#define KS8695_MEM_SIZE                    KS8695_SDRAM_SIZE
-#define KS8695_MEM_START           KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE      0x03800000
-#define KS8695_PCMCIA_IO_SIZE      0x00040000
-
-#define KS8695_IO_BASE             0x03FF0000
-#define KS8695_IO_SIZE             0x00010000
-
-#define KS8695_SYSTEN_CONFIG       0x00
-#define KS8695_SYSTEN_BUS_CLOCK            0x04
-
-#define KS8695_FLASH_START         0x02800000
-#define KS8695_FLASH_SIZE          0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0                    0x4000
-#define KS8695_IO_CTRL1                    0x4004
-#define KS8695_IO_CTRL2                    0x4008
-#define KS8695_IO_CTRL3                    0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0           0x4010
-#define KS8695_MEM_CTRL1           0x4014
-#define KS8695_MEM_CTRL2           0x4018
-#define KS8695_MEM_CTRL3           0x401C
-#define KS8695_MEM_GENERAL         0x4020
-#define KS8695_SDRAM_CTRL0         0x4030
-#define KS8695_SDRAM_CTRL1         0x4034
-#define KS8695_SDRAM_GENERAL       0x4038
-#define KS8695_SDRAM_BUFFER        0x403C
-#define KS8695_SDRAM_REFRESH       0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX          0x6000
-#define KS8695_WAN_DMA_RX          0x6004
-#define KS8695_WAN_DMA_TX_START            0x6008
-#define KS8695_WAN_DMA_RX_START            0x600C
-#define KS8695_WAN_TX_LIST         0x6010
-#define KS8695_WAN_RX_LIST         0x6014
-#define KS8695_WAN_MAC_LOW         0x6018
-#define KS8695_WAN_MAC_HIGH        0x601C
-#define KS8695_WAN_MAC_ELOW        0x6080
-#define KS8695_WAN_MAC_EHIGH       0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX          0x8000
-#define KS8695_LAN_DMA_RX          0x8004
-#define KS8695_LAN_DMA_TX_START            0x8008
-#define KS8695_LAN_DMA_RX_START            0x800C
-#define KS8695_LAN_TX_LIST         0x8010
-#define KS8695_LAN_RX_LIST         0x8014
-#define KS8695_LAN_MAC_LOW         0x8018
-#define KS8695_LAN_MAC_HIGH        0x801C
-#define KS8695_LAN_MAC_ELOW        0X8080
-#define KS8695_LAN_MAC_EHIGH       0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX         0xA000
-#define KS8695_HPNA_DMA_RX         0xA004
-#define KS8695_HPNA_DMA_TX_START    0xA008
-#define KS8695_HPNA_DMA_RX_START    0xA00C
-#define KS8695_HPNA_TX_LIST        0xA010
-#define KS8695_HPNA_RX_LIST        0xA014
-#define KS8695_HPNA_MAC_LOW        0xA018
-#define KS8695_HPNA_MAC_HIGH       0xA01C
-#define KS8695_HPNA_MAC_ELOW       0xA080
-#define KS8695_HPNA_MAC_EHIGH      0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER      0xE000
-#define KS8695_UART_TX_HOLDING     0xE004
-
-#define KS8695_UART_FIFO_CTRL      0xE008
-#define KS8695_UART_FIFO_TRIG01            0x00
-#define KS8695_UART_FIFO_TRIG04            0x80
-#define KS8695_UART_FIFO_TXRST     0x03
-#define KS8695_UART_FIFO_RXRST     0x02
-#define KS8695_UART_FIFO_FEN       0x01
-
-#define KS8695_UART_LINE_CTRL      0xE00C
-#define KS8695_UART_LINEC_BRK      0x40
-#define KS8695_UART_LINEC_EPS      0x10
-#define KS8695_UART_LINEC_PEN      0x08
-#define KS8695_UART_LINEC_STP2     0x04
-#define KS8695_UART_LINEC_WLEN8            0x03
-#define KS8695_UART_LINEC_WLEN7            0x02
-#define KS8695_UART_LINEC_WLEN6            0x01
-#define KS8695_UART_LINEC_WLEN5            0x00
-
-#define KS8695_UART_MODEM_CTRL     0xE010
-#define KS8695_UART_MODEMC_RTS     0x02
-#define KS8695_UART_MODEMC_DTR     0x01
-
-#define KS8695_UART_LINE_STATUS            0xE014
-#define KS8695_UART_LINES_TXFE     0x20
-#define KS8695_UART_LINES_BE       0x10
-#define KS8695_UART_LINES_FE       0x08
-#define KS8695_UART_LINES_PE       0x04
-#define KS8695_UART_LINES_OE       0x02
-#define KS8695_UART_LINES_RXFE     0x01
-#define KS8695_UART_LINES_ANY      (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS    0xE018
-#define KS8695_UART_MODEM_DCD      0x80
-#define KS8695_UART_MODEM_DSR      0x20
-#define KS8695_UART_MODEM_CTS      0x10
-#define KS8695_UART_MODEM_DDCD     0x08
-#define KS8695_UART_MODEM_DDSR     0x02
-#define KS8695_UART_MODEM_DCTS     0x01
-#define UART8695_MODEM_ANY         0xFF
-
-#define KS8695_UART_DIVISOR        0xE01C
-#define KS8695_UART_STATUS         0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL           0xE200
-#define KS8695_INT_ENABLE          0xE204
-#define KS8695_INT_ENABLE_MODEM            0x0800
-#define KS8695_INT_ENABLE_ERR      0x0400
-#define KS8695_INT_ENABLE_RX       0x0200
-#define KS8695_INT_ENABLE_TX       0x0100
-
-#define KS8695_INT_STATUS          0xE208
-#define KS8695_INT_WAN_PRIORITY            0xE20C
-#define KS8695_INT_HPNA_PRIORITY    0xE210
-#define KS8695_INT_LAN_PRIORITY            0xE214
-#define KS8695_INT_TIMER_PRIORITY   0xE218
-#define KS8695_INT_UART_PRIORITY    0xE21C
-#define KS8695_INT_EXT_PRIORITY            0xE220
-#define KS8695_INT_CHAN_PRIORITY    0xE224
-#define KS8695_INT_BUSERROR_PRO            0xE228
-#define KS8695_INT_MASK_STATUS     0xE22C
-#define KS8695_FIQ_PEND_PRIORITY    0xE230
-#define KS8695_IRQ_PEND_PRIORITY    0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL          0xE400
-#define KS8695_TIMER1              0xE404
-#define KS8695_TIMER0              0xE408
-#define KS8695_TIMER1_PCOUNT       0xE40C
-#define KS8695_TIMER0_PCOUNT       0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE           0xE600
-#define KS8695_GPIO_CTRL           0xE604
-#define KS8695_GPIO_DATA           0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0        0xE800
-#define KS8695_SWITCH_CTRL1        0xE804
-#define KS8695_SWITCH_PORT1        0xE808
-#define KS8695_SWITCH_PORT2        0xE80C
-#define KS8695_SWITCH_PORT3        0xE810
-#define KS8695_SWITCH_PORT4        0xE814
-#define KS8695_SWITCH_PORT5        0xE818
-#define KS8695_SWITCH_AUTO0        0xE81C
-#define KS8695_SWITCH_AUTO1        0xE820
-#define KS8695_SWITCH_LUE_CTRL     0xE824
-#define KS8695_SWITCH_LUE_HIGH     0xE828
-#define KS8695_SWITCH_LUE_LOW      0xE82C
-#define KS8695_SWITCH_ADVANCED     0xE830
-
-#define KS8695_SWITCH_LPPM12       0xE874
-#define KS8695_SWITCH_LPPM34       0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH           0xE834
-#define KS8695_DSCP_LOW                    0xE838
-#define KS8695_SWITCH_MAC_HIGH     0xE83C
-#define KS8695_SWITCH_MAC_LOW      0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER      0xE844
-#define KS8695_MANAGE_DATA         0xE848
-#define KS8695_LAN12_POWERMAGR     0xE84C
-#define KS8695_LAN34_POWERMAGR     0xE850
-
-#define KS8695_DEVICE_ID           0xEA00
-#define KS8695_REVISION_ID         0xEA04
-
-#define KS8695_MISC_CONTROL        0xEA08
-#define KS8695_WAN_CONTROL         0xEA0C
-#define KS8695_WAN_POWERMAGR       0xEA10
-#define KS8695_WAN_PHY_CONTROL     0xEA14
-#define KS8695_WAN_PHY_STATUS      0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ            0x0
-#define KS8695_BUS_CLOCK_100MHZ            0x1
-#define KS8695_BUS_CLOCK_62MHZ     0x2
-#define KS8695_BUS_CLOCK_50MHZ     0x3
-#define KS8695_BUS_CLOCK_41MHZ     0x4
-#define KS8695_BUS_CLOCK_33MHZ     0x5
-#define KS8695_BUS_CLOCK_31MHZ     0x6
-#define KS8695_BUS_CLOCK_25MHZ     0x7
-
-/* -------------------------------------------------------------------------------
- *  definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0                   2
-#define KS8695_INT_EXT_INT1                   3
-#define KS8695_INT_EXT_INT2                   4
-#define KS8695_INT_EXT_INT3                   5
-#define KS8695_INT_TIMERINT0                  6
-#define KS8695_INT_TIMERINT1                  7
-#define KS8695_INT_UART_TX                    8
-#define KS8695_INT_UART_RX                    9
-#define KS8695_INT_UART_LINE_ERR              10
-#define KS8695_INT_UART_MODEMS                11
-#define KS8695_INT_LAN_STOP_RX                12
-#define KS8695_INT_LAN_STOP_TX                13
-#define KS8695_INT_LAN_BUF_RX_STATUS          14
-#define KS8695_INT_LAN_BUF_TX_STATUS          15
-#define KS8695_INT_LAN_RX_STATUS              16
-#define KS8695_INT_LAN_TX_STATUS              17
-#define KS8695_INT_HPAN_STOP_RX                       18
-#define KS8695_INT_HPNA_STOP_TX                       19
-#define KS8695_INT_HPNA_BUF_RX_STATUS         20
-#define KS8695_INT_HPNA_BUF_TX_STATUS         21
-#define KS8695_INT_HPNA_RX_STATUS             22
-#define KS8695_INT_HPNA_TX_STATUS             23
-#define KS8695_INT_BUS_ERROR                  24
-#define KS8695_INT_WAN_STOP_RX                25
-#define KS8695_INT_WAN_STOP_TX                26
-#define KS8695_INT_WAN_BUF_RX_STATUS          27
-#define KS8695_INT_WAN_BUF_TX_STATUS          28
-#define KS8695_INT_WAN_RX_STATUS              29
-#define KS8695_INT_WAN_TX_STATUS              30
-
-#define KS8695_INT_UART                               KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- *  Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0                       ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1                       ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2                       ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3                       ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0              ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1              ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX                ( 1 << KS8695_INT_UART_TX  )
-#define KS8695_INTMASK_UART_RX                ( 1 << KS8695_INT_UART_RX  )
-#define KS8695_INTMASK_UART_LINE_ERR          ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS            ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX            ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX            ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS          ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS          ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX           ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX           ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS         ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS         ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR              ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX            ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX            ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS          ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS          ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT                   0xFFFFFFFF
-#define MAXIRQNUM                             31
-
-/*
- *  Timer definitions
- *
- *  Use timer 1 & 2
- *  (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC                 25
-#define mSEC_1                         1000
-#define mSEC_10                                (mSEC_1 * 10)
-
-#endif
-
-/*     END */
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
deleted file mode 100644 (file)
index 42a52bc..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
deleted file mode 100644 (file)
index 7fec971..0000000
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
-       uint32_t gpdr0;
-       uint32_t gpdr1;
-       uint32_t gpdr2;
-       uint32_t res;
-       uint32_t gpddr0;
-       uint32_t gpddr1;
-       uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
-       uint32_t bcr;
-       uint32_t tpr;
-       uint32_t pr;
-       uint32_t dr;
-       uint32_t cr;
-       uint32_t sr;
-       uint32_t ccr;
-       uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
-       uint32_t ccid;
-       uint32_t csrst;
-       uint32_t pad0[2];
-       uint32_t cist;
-       uint32_t cistm;
-       uint32_t cgpio_ist;
-       uint32_t cgpio_istm;
-       uint32_t cgpio_ip;
-       uint32_t cgpio_im;
-       uint32_t caxi_bw;
-       uint32_t caxi_ps;
-       uint32_t cmux_md;
-       uint32_t cex_pin_st;
-       uint32_t cmlb;
-       uint32_t pad1[1];
-       uint32_t cusb;
-       uint32_t pad2[41];
-       uint32_t cbsc;
-       uint32_t cdcrc;
-       uint32_t cmsr0;
-       uint32_t cmsr1;
-       uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
-       uint32_t crpr;
-       uint32_t pad0;
-       uint32_t crwr;
-       uint32_t crsr;
-       uint32_t crda;
-       uint32_t crdb;
-       uint32_t crha;
-       uint32_t crpa;
-       uint32_t crpb;
-       uint32_t crhb;
-       uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
-       uint32_t load;
-       uint32_t value;
-       uint32_t control;
-       uint32_t intclr;
-       uint32_t ris;
-       uint32_t mis;
-       uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
-       /* Display settings */
-       uint32_t dcm0;
-       uint16_t pad00;
-       uint16_t htp;
-       uint16_t hdp;
-       uint16_t hdb;
-       uint16_t hsp;
-       uint8_t  hsw;
-       uint8_t  vsw;
-       uint16_t pad01;
-       uint16_t vtr;
-       uint16_t vsp;
-       uint16_t vdp;
-       uint16_t wx;
-       uint16_t wy;
-       uint16_t ww;
-       uint16_t wh;
-
-       /* Layer 0 */
-       uint32_t l0m;
-       uint32_t l0oa;
-       uint32_t l0da;
-       uint16_t l0dx;
-       uint16_t l0dy;
-
-       /* Layer 1 */
-       uint32_t l1m;
-       uint32_t cbda0;
-       uint32_t cbda1;
-       uint32_t pad02;
-
-       /* Layer 2 */
-       uint32_t l2m;
-       uint32_t l2oa0;
-       uint32_t l2da0;
-       uint32_t l2oa1;
-       uint32_t l2da1;
-       uint16_t l2dx;
-       uint16_t l2dy;
-
-       /* Layer 3 */
-       uint32_t l3m;
-       uint32_t l3oa0;
-       uint32_t l3da0;
-       uint32_t l3oa1;
-       uint32_t l3da1;
-       uint16_t l3dx;
-       uint16_t l3dy;
-
-       /* Layer 4 */
-       uint32_t l4m;
-       uint32_t l4oa0;
-       uint32_t l4da0;
-       uint32_t l4oa1;
-       uint32_t l4da1;
-       uint16_t l4dx;
-       uint16_t l4dy;
-
-       /* Layer 5 */
-       uint32_t l5m;
-       uint32_t l5oa0;
-       uint32_t l5da0;
-       uint32_t l5oa1;
-       uint32_t l5da1;
-       uint16_t l5dx;
-       uint16_t l5dy;
-
-       /* Cursor */
-       uint16_t cutc;
-       uint8_t  cpm;
-       uint8_t  csize;
-       uint32_t cuoa0;
-       uint16_t cux0;
-       uint16_t cuy0;
-       uint32_t cuoa1;
-       uint16_t cux1;
-       uint16_t cuy1;
-
-       /* Layer blending */
-       uint32_t l0bld;
-       uint32_t pad03;
-       uint32_t l0tc;
-       uint16_t l3tc;
-       uint16_t l2tc;
-       uint32_t pad04[15];
-
-       /* Display settings */
-       uint32_t dcm1;
-       uint32_t dcm2;
-       uint32_t dcm3;
-       uint32_t pad05;
-
-       /* Layer 0 extended */
-       uint32_t l0em;
-       uint16_t l0wx;
-       uint16_t l0wy;
-       uint16_t l0ww;
-       uint16_t l0wh;
-       uint32_t pad06;
-
-       /* Layer 1 extended */
-       uint32_t l1em;
-       uint16_t l1wx;
-       uint16_t l1wy;
-       uint16_t l1ww;
-       uint16_t l1wh;
-       uint32_t pad07;
-
-       /* Layer 2 extended */
-       uint32_t l2em;
-       uint16_t l2wx;
-       uint16_t l2wy;
-       uint16_t l2ww;
-       uint16_t l2wh;
-       uint32_t pad08;
-
-       /* Layer 3 extended */
-       uint32_t l3em;
-       uint16_t l3wx;
-       uint16_t l3wy;
-       uint16_t l3ww;
-       uint16_t l3wh;
-       uint32_t pad09;
-
-       /* Layer 4 extended */
-       uint32_t l4em;
-       uint16_t l4wx;
-       uint16_t l4wy;
-       uint16_t l4ww;
-       uint16_t l4wh;
-       uint32_t pad10;
-
-       /* Layer 5 extended */
-       uint32_t l5em;
-       uint16_t l5wx;
-       uint16_t l5wy;
-       uint16_t l5ww;
-       uint16_t l5wh;
-       uint32_t pad11;
-
-       /* Multi screen control */
-       uint32_t msc;
-       uint32_t pad12[3];
-       uint32_t dls;
-       uint32_t dbgc;
-
-       /* Layer blending */
-       uint32_t l1bld;
-       uint32_t l2bld;
-       uint32_t l3bld;
-       uint32_t l4bld;
-       uint32_t l5bld;
-       uint32_t pad13;
-
-       /* Extended transparency control */
-       uint32_t l0etc;
-       uint32_t l1etc;
-       uint32_t l2etc;
-       uint32_t l3etc;
-       uint32_t l4etc;
-       uint32_t l5etc;
-       uint32_t pad14[10];
-
-       /* YUV coefficients */
-       uint32_t l1ycr0;
-       uint32_t l1ycr1;
-       uint32_t l1ycg0;
-       uint32_t l1ycg1;
-       uint32_t l1ycb0;
-       uint32_t l1ycb1;
-       uint32_t pad15[130];
-
-       /* Layer palletes */
-       uint32_t l0pal[256];
-       uint32_t l1pal[256];
-       uint32_t pad16[256];
-       uint32_t l2pal[256];
-       uint32_t l3pal[256];
-       uint32_t pad17[256];
-
-       /* PWM settings */
-       uint32_t vpwmm;
-       uint16_t vpwms;
-       uint16_t vpwme;
-       uint32_t vpwmc;
-       uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
-       uint32_t vcm;
-       uint32_t csc;
-       uint32_t vcs;
-       uint32_t pad01;
-
-       uint32_t cbm;
-       uint32_t cboa;
-       uint32_t cbla;
-       uint16_t cihstr;
-       uint16_t civstr;
-       uint16_t cihend;
-       uint16_t civend;
-       uint32_t pad02;
-
-       uint32_t chp;
-       uint32_t cvp;
-       uint32_t pad03[4];
-
-       uint32_t clpf;
-       uint32_t pad04;
-       uint32_t cmss;
-       uint32_t cmds;
-       uint32_t pad05[12];
-
-       uint32_t rgbhc;
-       uint32_t rgbhen;
-       uint32_t rgbven;
-       uint32_t pad06;
-       uint32_t rgbs;
-       uint32_t pad07[11];
-
-       uint32_t rgbcmy;
-       uint32_t rgbcmcb;
-       uint32_t rgbcmcr;
-       uint32_t rgbcmb;
-       uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
-       uint32_t ys;
-       uint32_t xs;
-       uint32_t dxdy;
-       uint32_t xus;
-       uint32_t dxudy;
-       uint32_t xls;
-       uint32_t dxldy;
-       uint32_t usn;
-       uint32_t lsn;
-       uint32_t pad01[7];
-       uint32_t rs;
-       uint32_t drdx;
-       uint32_t drdy;
-       uint32_t gs;
-       uint32_t dgdx;
-       uint32_t dgdy;
-       uint32_t bs;
-       uint32_t dbdx;
-       uint32_t dbdy;
-       uint32_t pad02[7];
-       uint32_t zs;
-       uint32_t dzdx;
-       uint32_t dzdy;
-       uint32_t pad03[13];
-       uint32_t ss;
-       uint32_t dsdx;
-       uint32_t dsdy;
-       uint32_t ts;
-       uint32_t dtdx;
-       uint32_t dtdy;
-       uint32_t qs;
-       uint32_t dqdx;
-       uint32_t dqdy;
-       uint32_t pad04[23];
-       uint32_t lpn;
-       uint32_t lxs;
-       uint32_t lxde;
-       uint32_t lys;
-       uint32_t lyde;
-       uint32_t lzs;
-       uint32_t lzde;
-       uint32_t pad05[13];
-       uint32_t pxdc;
-       uint32_t pydc;
-       uint32_t pzdc;
-       uint32_t pad06[25];
-       uint32_t rxs;
-       uint32_t rys;
-       uint32_t rsizex;
-       uint32_t rsizey;
-       uint32_t pad07[12];
-       uint32_t saddr;
-       uint32_t sstride;
-       uint32_t srx;
-       uint32_t sry;
-       uint32_t daddr;
-       uint32_t dstride;
-       uint32_t drx;
-       uint32_t dry;
-       uint32_t brsizex;
-       uint32_t brsizey;
-       uint32_t tcolor;
-       uint32_t pad08[93];
-       uint32_t blpo;
-       uint32_t pad09[7];
-       uint32_t ctr;
-       uint32_t ifsr;
-       uint32_t ifcnt;
-       uint32_t sst;
-       uint32_t ds;
-       uint32_t pst;
-       uint32_t est;
-       uint32_t pad10;
-       uint32_t mdr0;
-       uint32_t mdr1;
-       uint32_t mdr2;
-       uint32_t mdr3;
-       uint32_t mdr4;
-       uint32_t pad14[2];
-       uint32_t mdr7;
-       uint32_t fbr;
-       uint32_t xres;
-       uint32_t zbr;
-       uint32_t tbr;
-       uint32_t pfbr;
-       uint32_t cxmin;
-       uint32_t cxmax;
-       uint32_t cymin;
-       uint32_t cymax;
-       uint32_t txs;
-       uint32_t tis;
-       uint32_t toa;
-       uint32_t sho;
-       uint32_t abr;
-       uint32_t pad15[2];
-       uint32_t fc;
-       uint32_t bc;
-       uint32_t alf;
-       uint32_t blp;
-       uint32_t pad16;
-       uint32_t tbc;
-       uint32_t pad11[42];
-       uint32_t lx0dc;
-       uint32_t ly0dc;
-       uint32_t lx1dc;
-       uint32_t ly1dc;
-       uint32_t pad12[12];
-       uint32_t x0dc;
-       uint32_t y0dc;
-       uint32_t x1dc;
-       uint32_t y1dc;
-       uint32_t x2dc;
-       uint32_t y2dc;
-       uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
-       uint32_t gctr;
-       uint32_t pad00[15];
-       uint32_t gmdr0;
-       uint32_t gmdr1;
-       uint32_t gmdr2;
-       uint32_t pad01[237];
-       uint32_t dfifog;
-       uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
-       uint32_t pad00[2];
-       uint32_t lts;
-       uint32_t pad01;
-       uint32_t lsta;
-       uint32_t pad02[3];
-       uint32_t ist;
-       uint32_t imask;
-       uint32_t pad03[6];
-       uint32_t lsa;
-       uint32_t lco;
-       uint32_t lreq;
-
-       uint32_t pad04[16*1024 - 19];
-       struct mb86r0x_gdc_dsp dsp0;
-       struct mb86r0x_gdc_dsp dsp1;
-       uint32_t pad05[4*1024 - 2];
-       uint32_t vccc;
-       uint32_t vcsr;
-       struct mb86r0x_gdc_cap cap0;
-       struct mb86r0x_gdc_cap cap1;
-       uint32_t pad06[4*1024];
-       uint32_t texture_base[16*1024];
-       struct mb86r0x_gdc_draw draw;
-       uint32_t pad07[7*1024];
-       struct mb86r0x_gdc_geom geom;
-       uint32_t pad08[7*1024];
-};
-
-/* mb86r0x ddr2c */
-struct mb86r0x_ddr2c {
-       uint16_t dric;
-       uint16_t dric1;
-       uint16_t dric2;
-       uint16_t drca;
-       uint16_t drcm;
-       uint16_t drcst1;
-       uint16_t drcst2;
-       uint16_t drcr;
-       uint16_t pad00[8];
-       uint16_t drcf;
-       uint16_t pad01[7];
-       uint16_t drasr;
-       uint16_t pad02[15];
-       uint16_t drims;
-       uint16_t pad03[7];
-       uint16_t dros;
-       uint16_t pad04;
-       uint16_t dribsodt1;
-       uint16_t dribsocd;
-       uint16_t dribsocd2;
-       uint16_t pad05[3];
-       uint16_t droaba;
-       uint16_t pad06[9];
-       uint16_t drobs;
-       uint16_t pad07[5];
-       uint16_t drimr1;
-       uint16_t drimr2;
-       uint16_t drimr3;
-       uint16_t drimr4;
-       uint16_t droisr1;
-       uint16_t droisr2;
-};
-
-/* mb86r0x memc */
-struct mb86r0x_memc {
-       uint32_t mcfmode[8];
-       uint32_t mcftim[8];
-       uint32_t mcfarea[8];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE              0xf3000000
-#define MB86R0x_GDC_BASE               0xf1fc0000
-#define MB86R0x_CCNT_BASE              0xfff42000
-#define MB86R0x_CAN0_BASE              0xfff54000
-#define MB86R0x_CAN1_BASE              0xfff55000
-#define MB86R0x_I2C0_BASE              0xfff56000
-#define MB86R0x_I2C1_BASE              0xfff57000
-#define MB86R0x_EHCI_BASE              0xfff80000
-#define MB86R0x_OHCI_BASE              0xfff81000
-#define MB86R0x_IRC1_BASE              0xfffb0000
-#define MB86R0x_MEMC_BASE              0xfffc0000
-#define MB86R0x_TIMER_BASE             0xfffe0000
-#define MB86R0x_UART0_BASE             0xfffe1000
-#define MB86R0x_UART1_BASE             0xfffe2000
-#define MB86R0x_IRCE_BASE              0xfffe4000
-#define MB86R0x_CRG_BASE               0xfffe7000
-#define MB86R0x_IRC0_BASE              0xfffe8000
-#define MB86R0x_GPIO_BASE              0xfffe9000
-#define MB86R0x_PWM0_BASE              0xfff41000
-#define MB86R0x_PWM1_BASE              0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ          (1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE           (1 << 7)
-#define MB86R0x_TIMER_MODE_MSK         (1 << 6)
-#define MB86R0x_TIMER_MODE_FR          (0 << 6)
-#define MB86R0x_TIMER_MODE_PD          (1 << 6)
-
-#define MB86R0x_TIMER_INT_EN           (1 << 5)
-#define MB86R0x_TIMER_PRS_MSK          (3 << 2)
-#define MB86R0x_TIMER_PRS_4S           (1 << 2)
-#define MB86R0x_TIMER_PRS_8S           (1 << 3)
-#define MB86R0x_TIMER_SIZE_32          (1 << 1)
-#define MB86R0x_TIMER_ONE_SHT          (1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY                (1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE       (0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49   (0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46   (1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37   (2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20   (3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47   (4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44   (5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36   (6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19   (7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39   (8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38   (9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30   (10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15   (11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI                (1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN         (1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD                (1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD          (MB86R0x_DDR2_DRCI_DRINI | \
-                                       MB86R0x_DDR2_DRCI_CKEN | \
-                                       MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT         (MB86R0x_DDR2_DRCI_DRINI | \
-                                       MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL       MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644 (file)
index 1eed7b1..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
-#define CONFIG_SYS_TCLK                (14745600)      /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK    (3250000)       /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP                     /* Enable mvmfp driver */
-#define MV_MFPR_BASE           PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE   PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6)        /* Bit 6 in UART_IER register
-                                               represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV                  1
-#define CONFIG_MV_I2C_REG              0xd4011000
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           0
-#define CONFIG_SYS_I2C_SLAVE           0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT                 1
-#define CONFIG_MMC                     1
-#define CONFIG_GENERIC_MMC             1
-#define CONFIG_SDHCI                   1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS  1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT   0x1000
-#define CONFIG_MMC_SDMA                        1
-#define CONFIG_MV_SDHCI                        1
-#define CONFIG_DOS_PARTITION           1
-#define CONFIG_EFI_PARTITION           1
-#define CONFIG_SYS_MMC_NUM             2
-#define CONFIG_SYS_MMC_BASE            {0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644 (file)
index 3ccdf8a..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
-       u8 pad0[0x0024];
-       u32 ccgr;       /*0x0024*/
-       u8 pad1[0x0200 - 0x024 - 4];
-       u32 wdtpcr;     /*0x0200*/
-       u8 pad2[0x1020 - 0x200 - 4];
-       u32 aprr;       /*0x1020*/
-       u32 acgr;       /*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
-       u8 pad0[0x0054];
-       u32 sd1;        /*0x0054*/
-       u8 pad1[0x00e0 - 0x054 - 4];
-       u32 sd3;        /*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
-       u32 uart0;      /*0x000*/
-       u32 uart1;      /*0x004*/
-       u32 gpio;       /*0x008*/
-       u8 pad0[0x02c - 0x08 - 4];
-       u32 twsi;       /*0x02c*/
-       u8 pad1[0x034 - 0x2c - 4];
-       u32 timers;     /*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
-       u32 chip_id;            /* Chip Id Reg */
-       u32 pad;
-       u32 cpu_conf;           /* CPU Conf Reg */
-       u32 pad1;
-       u32 cpu_sram_spd;       /* CPU SRAM Speed Reg */
-       u32 pad2;
-       u32 cpu_l2c_spd;        /* CPU L2cache Speed Conf */
-       u32 mcb_conf;           /* MCB Conf Reg */
-       u32 sys_boot_ctl;       /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
deleted file mode 100644 (file)
index e69de29..0000000
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644 (file)
index 7909d53..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD                (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD                (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL         (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA         (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7          (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6          (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5          (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4          (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3          (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2          (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1          (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0          (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD           (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK           (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD            (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP            (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX    117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644 (file)
index c3a71bf..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK  (1<<4)  /* Peripheral Clock Enable */
-#define APMU_AXI_CLK   (1<<3)  /* AXI Clock Enable*/
-#define APMU_PERI_RST  (1<<1)  /* Peripheral Reset */
-#define APMU_AXI_RST   (1<<0)  /* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE     0xB0000000
-#define PANTHEON_TIMER_BASE    0xD4014000
-#define PANTHEON_WD_TIMER_BASE 0xD4080000
-#define PANTHEON_APBC_BASE     0xD4015000
-#define PANTHEON_UART1_BASE    0xD4017000
-#define PANTHEON_UART2_BASE    0xD4018000
-#define PANTHEON_GPIO_BASE     0xD4019000
-#define PANTHEON_MFPR_BASE     0xD401E000
-#define PANTHEON_MPMU_BASE     0xD4050000
-#define PANTHEON_APMU_BASE     0xD4282800
-#define PANTHEON_CPU_BASE      0xD4282C00
-
-#endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644 (file)
index dfc3b1b..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE    0x0
-#define PSC_MDCTL_NEXT_SYNCRST         0x1
-#define PSC_MDCTL_NEXT_DISABLE         0x2
-#define PSC_MDCTL_NEXT_ENABLE          0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ                24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
-       SYS_PLL,
-       TDM_PLL,
-       ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
-       int pll;
-       int internal_osc;
-       unsigned long pll_freq;
-       unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int  lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
-       lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
-       lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644 (file)
index d458e0b..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS              4
-#define ASYNC_EMIF_MODE_NOR            0
-#define ASYNC_EMIF_MODE_NAND           1
-#define ASYNC_EMIF_MODE_ONENAND                2
-#define ASYNC_EMIF_PRESERVE            -1
-
-struct async_emif_config {
-       unsigned mode;
-       unsigned select_strobe;
-       unsigned extend_wait;
-       unsigned wr_setup;
-       unsigned wr_strobe;
-       unsigned wr_hold;
-       unsigned rd_setup;
-       unsigned rd_strobe;
-       unsigned rd_hold;
-       unsigned turn_around;
-       enum {
-               ASYNC_EMIF_8    = 0,
-               ASYNC_EMIF_16   = 1,
-               ASYNC_EMIF_32   = 2,
-       } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0                (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1                (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n)    (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC  0x83e70b13
-#define TNETV107X_KICK1_MAGIC  0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE                    0x01C00000
-#define TNETV107X_TPTC0_BASE                   0x01C10000
-#define TNETV107X_TPTC1_BASE                   0x01C10400
-#define TNETV107X_INTC_BASE                    0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE          0x08030000
-#define TNETV107X_INTD_BASE                    0x08038000
-#define TNETV107X_INTD_IPC_BASE                        0x08038000
-#define TNETV107X_INTD_FAST_BASE               0x08039000
-#define TNETV107X_INTD_ASYNC_BASE              0x0803A000
-#define TNETV107X_INTD_SLOW_BASE               0x0803B000
-#define TNETV107X_PKA_BASE                     0x08040000
-#define TNETV107X_RNG_BASE                     0x08044000
-#define TNETV107X_TIMER0_BASE                  0x08086500
-#define TNETV107X_TIMER1_BASE                  0x08086600
-#define TNETV107X_WDT0_ARM_BASE                        0x08086700
-#define TNETV107X_WDT1_DSP_BASE                        0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE         0x08087000
-#define TNETV107X_GPIO_BASE                    0x08088000
-#define TNETV107X_UART1_BASE                   0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE             0x08088500
-#define TNETV107X_SDIO0_BASE                   0x08088700
-#define TNETV107X_SDIO1_BASE                   0x08088800
-#define TNETV107X_MDIO_BASE                    0x08088900
-#define TNETV107X_KEYPAD_BASE                  0x08088A00
-#define TNETV107X_SSP_BASE                     0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE           0x0808A000
-#define TNETV107X_PSC_BASE                     0x0808B000
-#define TNETV107X_TDM0_BASE                    0x08100000
-#define TNETV107X_TDM1_BASE                    0x08100100
-#define TNETV107X_MCDMA_BASE                   0x08108000
-#define TNETV107X_UART0_DMA_BASE               0x08108200
-#define TNETV107X_USBSS_BASE                   0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE           0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE                0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE           0x0C000000
-#define TNETV107X_IMCOP_BASE                   0x01CC0000
-#define TNETV107X_MBX_LITE_BASE                        0x07000000
-#define TNETV107X_ETHSS_BASE                   0x0803C000
-#define TNETV107X_CPSW_BASE                    0x0803C000
-#define TNETV107X_SPF_BASE                     0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE              0x0803D000
-#define TNETV107X_VTP_CNTRL_0                  0x0803D800
-#define TNETV107X_VTP_CNTRL_1                  0x0803D900
-#define TNETV107X_UART2_DMA_BASE               0x08108400
-#define TNETV107X_INTERNAL_MEMORY              0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE     0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE     0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE     0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE     0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE           0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE                0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM                     0
-#define TNETV107X_LPSC_GEM                     1
-#define TNETV107X_LPSC_DDR2_PHY                        2
-#define TNETV107X_LPSC_TPCC                    3
-#define TNETV107X_LPSC_TPTC0                   4
-#define TNETV107X_LPSC_TPTC1                   5
-#define TNETV107X_LPSC_RAM                     6
-#define TNETV107X_LPSC_MBX_LITE                        7
-#define TNETV107X_LPSC_LCD                     8
-#define TNETV107X_LPSC_ETHSS                   9
-#define TNETV107X_LPSC_AEMIF                   10
-#define TNETV107X_LPSC_CHIP_CFG                        11
-#define TNETV107X_LPSC_TSC                     12
-#define TNETV107X_LPSC_ROM                     13
-#define TNETV107X_LPSC_UART2                   14
-#define TNETV107X_LPSC_PKTSEC                  15
-#define TNETV107X_LPSC_SECCTL                  16
-#define TNETV107X_LPSC_KEYMGR                  17
-#define TNETV107X_LPSC_KEYPAD                  18
-#define TNETV107X_LPSC_GPIO                    19
-#define TNETV107X_LPSC_MDIO                    20
-#define TNETV107X_LPSC_SDIO0                   21
-#define TNETV107X_LPSC_UART0                   22
-#define TNETV107X_LPSC_UART1                   23
-#define TNETV107X_LPSC_TIMER0                  24
-#define TNETV107X_LPSC_TIMER1                  25
-#define TNETV107X_LPSC_WDT_ARM                 26
-#define TNETV107X_LPSC_WDT_DSP                 27
-#define TNETV107X_LPSC_SSP                     28
-#define TNETV107X_LPSC_TDM0                    29
-#define TNETV107X_LPSC_VLYNQ                   30
-#define TNETV107X_LPSC_MCDMA                   31
-#define TNETV107X_LPSC_USB0                    32
-#define TNETV107X_LPSC_TDM1                    33
-#define TNETV107X_LPSC_DEBUGSS                 34
-#define TNETV107X_LPSC_ETHSS_RGMII             35
-#define TNETV107X_LPSC_SYSTEM                  36
-#define TNETV107X_LPSC_IMCOP                   37
-#define TNETV107X_LPSC_SPARE                   38
-#define TNETV107X_LPSC_SDIO1                   39
-#define TNETV107X_LPSC_USB1                    40
-#define TNETV107X_LPSC_USBSS                   41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST         42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST     43
-#define TNETV107X_LPSC_MAX                     44
-
-/* Interrupt controller */
-#define INTC_GLB_EN                    (TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN                   (TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0                   (TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE  TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644 (file)
index 3f832c4..0000000
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
-       unsigned char reg_index;
-       unsigned char mask_offset;
-       unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
-                       { reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
-       TNETV107X_PIN_ASR_A00,
-       TNETV107X_PIN_GPIO32,
-       TNETV107X_PIN_ASR_A01,
-       TNETV107X_PIN_GPIO33,
-       TNETV107X_PIN_ASR_A02,
-       TNETV107X_PIN_GPIO34,
-       TNETV107X_PIN_ASR_A03,
-       TNETV107X_PIN_GPIO35,
-       TNETV107X_PIN_ASR_A04,
-       TNETV107X_PIN_GPIO36,
-       TNETV107X_PIN_ASR_A05,
-       TNETV107X_PIN_GPIO37,
-       TNETV107X_PIN_ASR_A06,
-       TNETV107X_PIN_GPIO38,
-       TNETV107X_PIN_ASR_A07,
-       TNETV107X_PIN_GPIO39,
-       TNETV107X_PIN_ASR_A08,
-       TNETV107X_PIN_GPIO40,
-       TNETV107X_PIN_ASR_A09,
-       TNETV107X_PIN_GPIO41,
-       TNETV107X_PIN_ASR_A10,
-       TNETV107X_PIN_GPIO42,
-       TNETV107X_PIN_ASR_A11,
-       TNETV107X_PIN_BOOT_STRP_0,
-       TNETV107X_PIN_ASR_A12,
-       TNETV107X_PIN_BOOT_STRP_1,
-       TNETV107X_PIN_ASR_A13,
-       TNETV107X_PIN_GPIO43,
-       TNETV107X_PIN_ASR_A14,
-       TNETV107X_PIN_GPIO44,
-       TNETV107X_PIN_ASR_A15,
-       TNETV107X_PIN_GPIO45,
-       TNETV107X_PIN_ASR_A16,
-       TNETV107X_PIN_GPIO46,
-       TNETV107X_PIN_ASR_A17,
-       TNETV107X_PIN_GPIO47,
-       TNETV107X_PIN_ASR_A18,
-       TNETV107X_PIN_GPIO48,
-       TNETV107X_PIN_SDIO1_DATA3_0,
-       TNETV107X_PIN_ASR_A19,
-       TNETV107X_PIN_GPIO49,
-       TNETV107X_PIN_SDIO1_DATA2_0,
-       TNETV107X_PIN_ASR_A20,
-       TNETV107X_PIN_GPIO50,
-       TNETV107X_PIN_SDIO1_DATA1_0,
-       TNETV107X_PIN_ASR_A21,
-       TNETV107X_PIN_GPIO51,
-       TNETV107X_PIN_SDIO1_DATA0_0,
-       TNETV107X_PIN_ASR_A22,
-       TNETV107X_PIN_GPIO52,
-       TNETV107X_PIN_SDIO1_CMD_0,
-       TNETV107X_PIN_ASR_A23,
-       TNETV107X_PIN_GPIO53,
-       TNETV107X_PIN_SDIO1_CLK_0,
-       TNETV107X_PIN_ASR_BA_1,
-       TNETV107X_PIN_GPIO54,
-       TNETV107X_PIN_SYS_PLL_CLK,
-       TNETV107X_PIN_ASR_CS0,
-       TNETV107X_PIN_ASR_CS1,
-       TNETV107X_PIN_ASR_CS2,
-       TNETV107X_PIN_TDM_PLL_CLK,
-       TNETV107X_PIN_ASR_CS3,
-       TNETV107X_PIN_ETH_PHY_CLK,
-       TNETV107X_PIN_ASR_D00,
-       TNETV107X_PIN_GPIO55,
-       TNETV107X_PIN_ASR_D01,
-       TNETV107X_PIN_GPIO56,
-       TNETV107X_PIN_ASR_D02,
-       TNETV107X_PIN_GPIO57,
-       TNETV107X_PIN_ASR_D03,
-       TNETV107X_PIN_GPIO58,
-       TNETV107X_PIN_ASR_D04,
-       TNETV107X_PIN_GPIO59_0,
-       TNETV107X_PIN_ASR_D05,
-       TNETV107X_PIN_GPIO60_0,
-       TNETV107X_PIN_ASR_D06,
-       TNETV107X_PIN_GPIO61_0,
-       TNETV107X_PIN_ASR_D07,
-       TNETV107X_PIN_GPIO62_0,
-       TNETV107X_PIN_ASR_D08,
-       TNETV107X_PIN_GPIO63_0,
-       TNETV107X_PIN_ASR_D09,
-       TNETV107X_PIN_GPIO64_0,
-       TNETV107X_PIN_ASR_D10,
-       TNETV107X_PIN_SDIO1_DATA3_1,
-       TNETV107X_PIN_ASR_D11,
-       TNETV107X_PIN_SDIO1_DATA2_1,
-       TNETV107X_PIN_ASR_D12,
-       TNETV107X_PIN_SDIO1_DATA1_1,
-       TNETV107X_PIN_ASR_D13,
-       TNETV107X_PIN_SDIO1_DATA0_1,
-       TNETV107X_PIN_ASR_D14,
-       TNETV107X_PIN_SDIO1_CMD_1,
-       TNETV107X_PIN_ASR_D15,
-       TNETV107X_PIN_SDIO1_CLK_1,
-       TNETV107X_PIN_ASR_OE,
-       TNETV107X_PIN_BOOT_STRP_2,
-       TNETV107X_PIN_ASR_RNW,
-       TNETV107X_PIN_GPIO29_0,
-       TNETV107X_PIN_ASR_WAIT,
-       TNETV107X_PIN_GPIO30_0,
-       TNETV107X_PIN_ASR_WE,
-       TNETV107X_PIN_BOOT_STRP_3,
-       TNETV107X_PIN_ASR_WE_DQM0,
-       TNETV107X_PIN_GPIO31,
-       TNETV107X_PIN_LCD_PD17_0,
-       TNETV107X_PIN_ASR_WE_DQM1,
-       TNETV107X_PIN_ASR_BA0_0,
-       TNETV107X_PIN_VLYNQ_CLK,
-       TNETV107X_PIN_GPIO14,
-       TNETV107X_PIN_LCD_PD19_0,
-       TNETV107X_PIN_VLYNQ_RXD0,
-       TNETV107X_PIN_GPIO15,
-       TNETV107X_PIN_LCD_PD20_0,
-       TNETV107X_PIN_VLYNQ_RXD1,
-       TNETV107X_PIN_GPIO16,
-       TNETV107X_PIN_LCD_PD21_0,
-       TNETV107X_PIN_VLYNQ_TXD0,
-       TNETV107X_PIN_GPIO17,
-       TNETV107X_PIN_LCD_PD22_0,
-       TNETV107X_PIN_VLYNQ_TXD1,
-       TNETV107X_PIN_GPIO18,
-       TNETV107X_PIN_LCD_PD23_0,
-       TNETV107X_PIN_SDIO0_CLK,
-       TNETV107X_PIN_GPIO19,
-       TNETV107X_PIN_SDIO0_CMD,
-       TNETV107X_PIN_GPIO20,
-       TNETV107X_PIN_SDIO0_DATA0,
-       TNETV107X_PIN_GPIO21,
-       TNETV107X_PIN_SDIO0_DATA1,
-       TNETV107X_PIN_GPIO22,
-       TNETV107X_PIN_SDIO0_DATA2,
-       TNETV107X_PIN_GPIO23,
-       TNETV107X_PIN_SDIO0_DATA3,
-       TNETV107X_PIN_GPIO24,
-       TNETV107X_PIN_EMU0,
-       TNETV107X_PIN_EMU1,
-       TNETV107X_PIN_RTCK,
-       TNETV107X_PIN_TRST_N,
-       TNETV107X_PIN_TCK,
-       TNETV107X_PIN_TDI,
-       TNETV107X_PIN_TDO,
-       TNETV107X_PIN_TMS,
-       TNETV107X_PIN_TDM1_CLK,
-       TNETV107X_PIN_TDM1_RX,
-       TNETV107X_PIN_TDM1_TX,
-       TNETV107X_PIN_TDM1_FS,
-       TNETV107X_PIN_KEYPAD_R0,
-       TNETV107X_PIN_KEYPAD_R1,
-       TNETV107X_PIN_KEYPAD_R2,
-       TNETV107X_PIN_KEYPAD_R3,
-       TNETV107X_PIN_KEYPAD_R4,
-       TNETV107X_PIN_KEYPAD_R5,
-       TNETV107X_PIN_KEYPAD_R6,
-       TNETV107X_PIN_GPIO12,
-       TNETV107X_PIN_KEYPAD_R7,
-       TNETV107X_PIN_GPIO10,
-       TNETV107X_PIN_KEYPAD_C0,
-       TNETV107X_PIN_KEYPAD_C1,
-       TNETV107X_PIN_KEYPAD_C2,
-       TNETV107X_PIN_KEYPAD_C3,
-       TNETV107X_PIN_KEYPAD_C4,
-       TNETV107X_PIN_KEYPAD_C5,
-       TNETV107X_PIN_KEYPAD_C6,
-       TNETV107X_PIN_GPIO13,
-       TNETV107X_PIN_TEST_CLK_IN,
-       TNETV107X_PIN_KEYPAD_C7,
-       TNETV107X_PIN_GPIO11,
-       TNETV107X_PIN_SSP0_0,
-       TNETV107X_PIN_SCC_DCLK,
-       TNETV107X_PIN_LCD_PD20_1,
-       TNETV107X_PIN_SSP0_1,
-       TNETV107X_PIN_SCC_CS_N,
-       TNETV107X_PIN_LCD_PD21_1,
-       TNETV107X_PIN_SSP0_2,
-       TNETV107X_PIN_SCC_D,
-       TNETV107X_PIN_LCD_PD22_1,
-       TNETV107X_PIN_SSP0_3,
-       TNETV107X_PIN_SCC_RESETN,
-       TNETV107X_PIN_LCD_PD23_1,
-       TNETV107X_PIN_SSP1_0,
-       TNETV107X_PIN_GPIO25,
-       TNETV107X_PIN_UART2_CTS,
-       TNETV107X_PIN_SSP1_1,
-       TNETV107X_PIN_GPIO26,
-       TNETV107X_PIN_UART2_RD,
-       TNETV107X_PIN_SSP1_2,
-       TNETV107X_PIN_GPIO27,
-       TNETV107X_PIN_UART2_RTS,
-       TNETV107X_PIN_SSP1_3,
-       TNETV107X_PIN_GPIO28,
-       TNETV107X_PIN_UART2_TD,
-       TNETV107X_PIN_UART0_CTS,
-       TNETV107X_PIN_UART0_RD,
-       TNETV107X_PIN_UART0_RTS,
-       TNETV107X_PIN_UART0_TD,
-       TNETV107X_PIN_UART1_RD,
-       TNETV107X_PIN_UART1_TD,
-       TNETV107X_PIN_LCD_AC_NCS,
-       TNETV107X_PIN_LCD_HSYNC_RNW,
-       TNETV107X_PIN_LCD_VSYNC_A0,
-       TNETV107X_PIN_LCD_MCLK,
-       TNETV107X_PIN_LCD_PD16_0,
-       TNETV107X_PIN_LCD_PCLK_E,
-       TNETV107X_PIN_LCD_PD00,
-       TNETV107X_PIN_LCD_PD01,
-       TNETV107X_PIN_LCD_PD02,
-       TNETV107X_PIN_LCD_PD03,
-       TNETV107X_PIN_LCD_PD04,
-       TNETV107X_PIN_LCD_PD05,
-       TNETV107X_PIN_LCD_PD06,
-       TNETV107X_PIN_LCD_PD07,
-       TNETV107X_PIN_LCD_PD08,
-       TNETV107X_PIN_GPIO59_1,
-       TNETV107X_PIN_LCD_PD09,
-       TNETV107X_PIN_GPIO60_1,
-       TNETV107X_PIN_LCD_PD10,
-       TNETV107X_PIN_ASR_BA0_1,
-       TNETV107X_PIN_GPIO61_1,
-       TNETV107X_PIN_LCD_PD11,
-       TNETV107X_PIN_GPIO62_1,
-       TNETV107X_PIN_LCD_PD12,
-       TNETV107X_PIN_GPIO63_1,
-       TNETV107X_PIN_LCD_PD13,
-       TNETV107X_PIN_GPIO64_1,
-       TNETV107X_PIN_LCD_PD14,
-       TNETV107X_PIN_GPIO29_1,
-       TNETV107X_PIN_LCD_PD15,
-       TNETV107X_PIN_GPIO30_1,
-       TNETV107X_PIN_EINT0,
-       TNETV107X_PIN_GPIO08,
-       TNETV107X_PIN_EINT1,
-       TNETV107X_PIN_GPIO09,
-       TNETV107X_PIN_GPIO00,
-       TNETV107X_PIN_LCD_PD20_2,
-       TNETV107X_PIN_TDM_CLK_IN_2,
-       TNETV107X_PIN_GPIO01,
-       TNETV107X_PIN_LCD_PD21_2,
-       TNETV107X_PIN_24M_CLK_OUT_1,
-       TNETV107X_PIN_GPIO02,
-       TNETV107X_PIN_LCD_PD22_2,
-       TNETV107X_PIN_GPIO03,
-       TNETV107X_PIN_LCD_PD23_2,
-       TNETV107X_PIN_GPIO04,
-       TNETV107X_PIN_LCD_PD16_1,
-       TNETV107X_PIN_USB0_RXERR,
-       TNETV107X_PIN_GPIO05,
-       TNETV107X_PIN_LCD_PD17_1,
-       TNETV107X_PIN_TDM_CLK_IN_1,
-       TNETV107X_PIN_GPIO06,
-       TNETV107X_PIN_LCD_PD18,
-       TNETV107X_PIN_24M_CLK_OUT_2,
-       TNETV107X_PIN_GPIO07,
-       TNETV107X_PIN_LCD_PD19_1,
-       TNETV107X_PIN_USB1_RXERR,
-       TNETV107X_PIN_ETH_PLL_CLK,
-       TNETV107X_PIN_MDIO,
-       TNETV107X_PIN_MDC,
-       TNETV107X_PIN_AIC_MUTE_STAT_N,
-       TNETV107X_PIN_TDM0_CLK,
-       TNETV107X_PIN_AIC_HNS_EN_N,
-       TNETV107X_PIN_TDM0_FS,
-       TNETV107X_PIN_AIC_HDS_EN_STAT_N,
-       TNETV107X_PIN_TDM0_TX,
-       TNETV107X_PIN_AIC_HNF_EN_STAT_N,
-       TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
index b0c26e5..e5bcaea 100644 (file)
@@ -15,9 +15,6 @@
 #include <common.h>
 #include <linux/kbuild.h>
 
-#if defined(CONFIG_MB86R0x)
-#include <asm/arch/mb86r0x.h>
-#endif
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
        || defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
@@ -27,8 +24,6 @@ int main(void)
 {
        /*
         * TODO : Check if each entry in this file is really necessary.
-        *   - struct mb86r0x_ddr2
-        *   - struct mb86r0x_memc
         *   - struct esdramc_regs
         *   - struct max_regs
         *   - struct aips_regs
@@ -40,47 +35,6 @@ int main(void)
         * code. Is it better to define the macros directly in headers?
         */
 
-#if defined(CONFIG_MB86R0x)
-       /* ddr2 controller */
-       DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
-       DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
-       DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
-       DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
-       DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
-       DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
-       DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
-       DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
-       DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
-       DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
-       DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
-       DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
-       DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
-       DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
-       DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
-       /* clock reset generator */
-       DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
-       DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
-       DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
-       DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
-       DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
-       DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
-       /* chip control module */
-       DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
-       /* external bus interface */
-       DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
-       DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
-       DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
-       DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
-       DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
-       DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
-       DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
-       DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
-       DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-#endif
-
 #if defined(CONFIG_MX25)
        /* Clock Control Module */
        DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
index 613f04d..6827721 100644 (file)
@@ -21,10 +21,6 @@ config TARGET_CAM_ENC_4XX
        bool "CAM ENC 4xx board"
        select SUPPORT_SPL
 
-config TARGET_HAWKBOARD
-       bool "Hawkboard"
-       select SUPPORT_SPL
-
 config TARGET_DAVINCI_DM355EVM
        bool "DM355 EVM board"
 
index 3a8e2b1..8615248 100644 (file)
@@ -24,25 +24,25 @@ config SYS_MALLOC_F_LEN
        default 0x1800
 
 config USE_PRIVATE_LIBGCC
-       default y if SPL_BUILD
+       default y
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 config DM_SPI
-       default y if !SPL_BUILD
+       default y
 
 config DM_SPI_FLASH
-       default y if !SPL_BUILD
+       default y
 
 config DM_I2C
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 source "arch/arm/mach-tegra/tegra20/Kconfig"
 source "arch/arm/mach-tegra/tegra30/Kconfig"
diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig
deleted file mode 100644 (file)
index f674894..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DKB
-
-config SYS_BOARD
-       default "dkb"
-
-config SYS_VENDOR
-       default "Marvell"
-
-config SYS_SOC
-       default "pantheon"
-
-config SYS_CONFIG_NAME
-       default "dkb"
-
-endif
diff --git a/board/Marvell/dkb/MAINTAINERS b/board/Marvell/dkb/MAINTAINERS
deleted file mode 100644 (file)
index c272b7a..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-DKB BOARD
-M:     Lei Wen <leiwen@marvell.com>
-S:     Maintained
-F:     board/Marvell/dkb/
-F:     include/configs/dkb.h
-F:     configs/dkb_defconfig
diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile
deleted file mode 100644 (file)
index 9d88579..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := dkb.o
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
deleted file mode 100644 (file)
index c0c3125..0000000
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mvmfp.h>
-#include <i2c.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/cpu.h>
-#ifdef CONFIG_GENERIC_MMC
-#include <sdhci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-       u32 mfp_cfg[] = {
-               /* Enable Console on UART2 */
-               MFP47_UART2_RXD,
-               MFP48_UART2_TXD,
-
-               /* I2C */
-               MFP53_CI2C_SCL,
-               MFP54_CI2C_SDA,
-
-               /* MMC1 */
-               MFP_MMC1_DAT7,
-               MFP_MMC1_DAT6,
-               MFP_MMC1_DAT5,
-               MFP_MMC1_DAT4,
-               MFP_MMC1_DAT3,
-               MFP_MMC1_DAT2,
-               MFP_MMC1_DAT1,
-               MFP_MMC1_DAT0,
-               MFP_MMC1_CMD,
-               MFP_MMC1_CLK,
-               MFP_MMC1_CD,
-               MFP_MMC1_WP,
-
-               MFP_EOC         /*End of configureation*/
-       };
-       /* configure MFP's */
-       mfp_config(mfp_cfg);
-
-       return 0;
-}
-
-int board_init(void)
-{
-       /* arch number of Board */
-       gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
-       return 0;
-}
-
-#ifdef CONFIG_GENERIC_MMC
-#define I2C_SLAVE_ADDR 0x34
-#define LDO13_REG      0x28
-#define LDO_V30                0x6
-#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
-#define LDO_EN         0x1
-int board_mmc_init(bd_t *bd)
-{
-       ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
-       u8 i, data;
-
-       /* set LDO 13 to 3.0v */
-       data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
-       i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
-
-       for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
-               if (mv_sdh_init(mmc_base_address[i], 0, 0,
-                               SDHCI_QUIRK_32BIT_DMA_ADDR))
-                       return 1;
-       }
-
-       return 0;
-}
-#endif
diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig
deleted file mode 100644 (file)
index de87d5b..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CM4008
-
-config SYS_BOARD
-       default "cm4008"
-
-config SYS_SOC
-       default "ks8695"
-
-config SYS_CONFIG_NAME
-       default "cm4008"
-
-endif
diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS
deleted file mode 100644 (file)
index 5f08bc3..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-CM4008 BOARD
-M:     Greg Ungerer <greg.ungerer@opengear.com>
-S:     Maintained
-F:     board/cm4008/
-F:     include/configs/cm4008.h
-F:     configs/cm4008_defconfig
diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile
deleted file mode 100644 (file)
index 04b1529..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := cm4008.o flash.o
diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c
deleted file mode 100644 (file)
index 740e164..0000000
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define        ks8695_read(a)    *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define        ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
-       char *sp = (char *) 0x0201c020;
-       char *ep;
-       int len;
-
-       /* Check if "erase" push button is depressed */
-       if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
-               printf("### Entering network recovery mode...\n");
-               setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
-               setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
-               setenv("bootdelay", "2");
-               return 0;
-       }
-
-       /* Check for flash based kernel boot args to use as default */
-       for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
-               ;
-
-       if ((len > 0) && (len <1024))
-               setenv("bootargs", sp);
-
-       return 0;
-}
-
-int board_late_init (void)
-{
-       return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-       return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
-       /* arch number of CM4008 */
-       gd->bd->bi_arch_number = 624;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = 0x00000100;
-
-       /* power down all but port 0 on the switch */
-       ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
-       ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
-       return 0;
-}
-
-int dram_init (void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-
-       return (0);
-}
diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk
deleted file mode 100644 (file)
index 0d5923b..0000000
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
deleted file mode 100644 (file)
index 8315a57..0000000
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-       int i;
-       ulong size = 0;
-
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-               switch (i) {
-               case 0:
-                       flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
-                       flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-                       break;
-               case 1:
-                       /* ignore for now */
-                       flash_info[i].flash_id = FLASH_UNKNOWN;
-                       break;
-               default:
-                       panic ("configured too many flash banks!\n");
-                       break;
-               }
-               size += flash_info[i].size;
-       }
-
-       /* Protect monitor and environment sectors
-        */
-       flash_protect (FLAG_PROTECT_SET,
-                      CONFIG_SYS_FLASH_BASE,
-                      CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
-                      &flash_info[0]);
-
-       return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN)
-               return;
-
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-                       info->protect[i] = 0;
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_INTEL:
-               printf ("INTEL ");
-               break;
-       default:
-               printf ("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_28F128J3A:
-               printf ("28F128J3A\n");
-               break;
-       default:
-               printf ("Unknown Chip Type\n");
-               break;
-       }
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf ("\n   ");
-               printf (" %08lX%s",
-                       info->start[i], info->protect[i] ? " (RO)" : "     ");
-       }
-       printf ("\n");
-       return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
-       volatile unsigned char value;
-
-       /* Write auto select command: read Manufacturer ID */
-       addr[0x5555] = 0xAA;
-       addr[0x2AAA] = 0x55;
-       addr[0x5555] = 0x90;
-
-       mb ();
-       value = addr[0];
-
-       switch (value) {
-
-       case (unsigned char)INTEL_MANUFACT:
-               info->flash_id = FLASH_MAN_INTEL;
-               break;
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               addr[0] = 0xFF; /* restore read mode */
-               return (0);     /* no or unknown flash  */
-       }
-
-       mb ();
-       value = addr[2];        /* device ID            */
-
-       switch (value) {
-
-       case (unsigned char)INTEL_ID_28F640J3A:
-               info->flash_id += FLASH_28F640J3A;
-               info->sector_count = 64;
-               info->size = 0x00800000;
-               break;          /* => 8 MB     */
-
-       case (unsigned char)INTEL_ID_28F128J3A:
-               info->flash_id += FLASH_28F128J3A;
-               info->sector_count = 128;
-               info->size = 0x01000000;
-               break;          /* => 16 MB     */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               break;
-       }
-
-       if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-               printf ("** ERROR: sector count %d > max (%d) **\n",
-                       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-               info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-       }
-
-       addr[0] = 0xFF; /* restore read mode */
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-       int prot, sect;
-       ulong type;
-       int rcode = 0;
-       ulong start;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       type = (info->flash_id & FLASH_VENDMASK);
-       if ((type != FLASH_MAN_INTEL)) {
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot)
-               printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-       else
-               printf ("\n");
-
-       /* Disable interrupts which might cause a timeout here */
-       disable_interrupts();
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       volatile unsigned char *addr;
-                       unsigned char status;
-
-                       printf ("Erasing sector %2d ... ", sect);
-
-                       /* arm simple, non interrupt dependent timer */
-                       start = get_timer(0);
-
-                       addr = (volatile unsigned char *) (info->start[sect]);
-                       *addr = 0x50;   /* clear status register */
-                       *addr = 0x20;   /* erase setup */
-                       *addr = 0xD0;   /* erase confirm */
-
-                       while (((status = *addr) & 0x80) != 0x80) {
-                               if (get_timer(start) >
-                                   CONFIG_SYS_FLASH_ERASE_TOUT) {
-                                       printf ("Timeout\n");
-                                       *addr = 0xB0;   /* suspend erase */
-                                       *addr = 0xFF;   /* reset to read mode */
-                                       rcode = 1;
-                                       break;
-                               }
-                       }
-
-                       *addr = 0x50;   /* clear status register cmd */
-                       *addr = 0xFF;   /* resest to read mode */
-
-                       printf (" done\n");
-               }
-       }
-       return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-       ulong cp, wp;
-       unsigned char data;
-       int count, i, l, rc, port_width;
-
-       if (info->flash_id == FLASH_UNKNOWN)
-               return 4;
-
-       wp = addr;
-       port_width = 1;
-
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i = 0, cp = wp; i < l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *) cp);
-               }
-               for (; i < port_width && cnt > 0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt == 0 && i < port_width; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *) cp);
-               }
-
-               if ((rc = write_data (info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += port_width;
-       }
-
-       /*
-        * handle word aligned part
-        */
-       count = 0;
-       while (cnt >= port_width) {
-               data = 0;
-               for (i = 0; i < port_width; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_data (info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += port_width;
-               cnt -= port_width;
-               if (count++ > 0x800) {
-                       spin_wheel ();
-                       count = 0;
-               }
-       }
-
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i < port_width; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *) cp);
-       }
-
-       return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
-       volatile unsigned char *addr = (volatile unsigned char *) dest;
-       ulong status;
-       ulong start;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*addr & data) != data) {
-               printf ("not erased at %08lx (%lx)\n", (ulong) addr,
-                       (ulong) * addr);
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       disable_interrupts();
-
-       *addr = 0x40;   /* write setup */
-       *addr = data;
-
-       /* arm simple, non interrupt dependent timer */
-       start = get_timer(0);
-
-       /* wait while polling the status register */
-       while (((status = *addr) & 0x80) != 0x80) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       *addr = 0xFF;   /* restore read mode */
-                       return (1);
-               }
-       }
-
-       *addr = 0xFF;   /* restore read mode */
-
-       return (0);
-}
-
-void inline spin_wheel (void)
-{
-       static int p = 0;
-       static char w[] = "\\/-";
-
-       printf ("\010%c", w[p]);
-       (++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig
deleted file mode 100644 (file)
index 99e675b..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CM41XX
-
-config SYS_BOARD
-       default "cm41xx"
-
-config SYS_SOC
-       default "ks8695"
-
-config SYS_CONFIG_NAME
-       default "cm41xx"
-
-endif
diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS
deleted file mode 100644 (file)
index f10eeb5..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-CM41XX BOARD
-#M:    -
-S:     Maintained
-F:     board/cm41xx/
-F:     include/configs/cm41xx.h
-F:     configs/cm41xx_defconfig
diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile
deleted file mode 100644 (file)
index b71ea05..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := cm41xx.o flash.o
diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c
deleted file mode 100644 (file)
index eabad48..0000000
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define        ks8695_read(a)    *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define        ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
-       char *sp = (char *) 0x0201c020;
-       char *ep;
-       int len;
-
-       /* Check if "erase" push button is depressed */
-       if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
-               printf("### Entering network recovery mode...\n");
-               setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
-               setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
-               setenv("bootdelay", "2");
-               return 0;
-       }
-
-       /* Check for flash based kernel boot args to use as default */
-       for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
-               ;
-
-       if ((len > 0) && (len <1024))
-               setenv("bootargs", sp);
-
-       return 0;
-}
-
-int board_late_init (void)
-{
-       return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-       return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
-       /* arch number of CM41xx */
-       gd->bd->bi_arch_number = 672;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = 0x00000100;
-
-       /* power down all but port 0 on the switch */
-       ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
-       ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
-       return 0;
-}
-
-int dram_init (void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-
-       return (0);
-}
diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk
deleted file mode 100644 (file)
index 0d5923b..0000000
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
deleted file mode 100644 (file)
index 8315a57..0000000
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-       int i;
-       ulong size = 0;
-
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-               switch (i) {
-               case 0:
-                       flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
-                       flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-                       break;
-               case 1:
-                       /* ignore for now */
-                       flash_info[i].flash_id = FLASH_UNKNOWN;
-                       break;
-               default:
-                       panic ("configured too many flash banks!\n");
-                       break;
-               }
-               size += flash_info[i].size;
-       }
-
-       /* Protect monitor and environment sectors
-        */
-       flash_protect (FLAG_PROTECT_SET,
-                      CONFIG_SYS_FLASH_BASE,
-                      CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
-                      &flash_info[0]);
-
-       return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN)
-               return;
-
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-                       info->protect[i] = 0;
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_INTEL:
-               printf ("INTEL ");
-               break;
-       default:
-               printf ("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_28F128J3A:
-               printf ("28F128J3A\n");
-               break;
-       default:
-               printf ("Unknown Chip Type\n");
-               break;
-       }
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf ("\n   ");
-               printf (" %08lX%s",
-                       info->start[i], info->protect[i] ? " (RO)" : "     ");
-       }
-       printf ("\n");
-       return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
-       volatile unsigned char value;
-
-       /* Write auto select command: read Manufacturer ID */
-       addr[0x5555] = 0xAA;
-       addr[0x2AAA] = 0x55;
-       addr[0x5555] = 0x90;
-
-       mb ();
-       value = addr[0];
-
-       switch (value) {
-
-       case (unsigned char)INTEL_MANUFACT:
-               info->flash_id = FLASH_MAN_INTEL;
-               break;
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               addr[0] = 0xFF; /* restore read mode */
-               return (0);     /* no or unknown flash  */
-       }
-
-       mb ();
-       value = addr[2];        /* device ID            */
-
-       switch (value) {
-
-       case (unsigned char)INTEL_ID_28F640J3A:
-               info->flash_id += FLASH_28F640J3A;
-               info->sector_count = 64;
-               info->size = 0x00800000;
-               break;          /* => 8 MB     */
-
-       case (unsigned char)INTEL_ID_28F128J3A:
-               info->flash_id += FLASH_28F128J3A;
-               info->sector_count = 128;
-               info->size = 0x01000000;
-               break;          /* => 16 MB     */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               break;
-       }
-
-       if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-               printf ("** ERROR: sector count %d > max (%d) **\n",
-                       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-               info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-       }
-
-       addr[0] = 0xFF; /* restore read mode */
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-       int prot, sect;
-       ulong type;
-       int rcode = 0;
-       ulong start;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       type = (info->flash_id & FLASH_VENDMASK);
-       if ((type != FLASH_MAN_INTEL)) {
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot)
-               printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-       else
-               printf ("\n");
-
-       /* Disable interrupts which might cause a timeout here */
-       disable_interrupts();
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       volatile unsigned char *addr;
-                       unsigned char status;
-
-                       printf ("Erasing sector %2d ... ", sect);
-
-                       /* arm simple, non interrupt dependent timer */
-                       start = get_timer(0);
-
-                       addr = (volatile unsigned char *) (info->start[sect]);
-                       *addr = 0x50;   /* clear status register */
-                       *addr = 0x20;   /* erase setup */
-                       *addr = 0xD0;   /* erase confirm */
-
-                       while (((status = *addr) & 0x80) != 0x80) {
-                               if (get_timer(start) >
-                                   CONFIG_SYS_FLASH_ERASE_TOUT) {
-                                       printf ("Timeout\n");
-                                       *addr = 0xB0;   /* suspend erase */
-                                       *addr = 0xFF;   /* reset to read mode */
-                                       rcode = 1;
-                                       break;
-                               }
-                       }
-
-                       *addr = 0x50;   /* clear status register cmd */
-                       *addr = 0xFF;   /* resest to read mode */
-
-                       printf (" done\n");
-               }
-       }
-       return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-       ulong cp, wp;
-       unsigned char data;
-       int count, i, l, rc, port_width;
-
-       if (info->flash_id == FLASH_UNKNOWN)
-               return 4;
-
-       wp = addr;
-       port_width = 1;
-
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i = 0, cp = wp; i < l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *) cp);
-               }
-               for (; i < port_width && cnt > 0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt == 0 && i < port_width; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *) cp);
-               }
-
-               if ((rc = write_data (info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += port_width;
-       }
-
-       /*
-        * handle word aligned part
-        */
-       count = 0;
-       while (cnt >= port_width) {
-               data = 0;
-               for (i = 0; i < port_width; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_data (info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += port_width;
-               cnt -= port_width;
-               if (count++ > 0x800) {
-                       spin_wheel ();
-                       count = 0;
-               }
-       }
-
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i < port_width; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *) cp);
-       }
-
-       return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
-       volatile unsigned char *addr = (volatile unsigned char *) dest;
-       ulong status;
-       ulong start;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*addr & data) != data) {
-               printf ("not erased at %08lx (%lx)\n", (ulong) addr,
-                       (ulong) * addr);
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       disable_interrupts();
-
-       *addr = 0x40;   /* write setup */
-       *addr = data;
-
-       /* arm simple, non interrupt dependent timer */
-       start = get_timer(0);
-
-       /* wait while polling the status register */
-       while (((status = *addr) & 0x80) != 0x80) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       *addr = 0xFF;   /* restore read mode */
-                       return (1);
-               }
-       }
-
-       *addr = 0xFF;   /* restore read mode */
-
-       return (0);
-}
-
-void inline spin_wheel (void)
-{
-       static int p = 0;
-       static char w[] = "\\/-";
-
-       printf ("\010%c", w[p]);
-       (++p == 3) ? (p = 0) : 0;
-}
index aadbfbc..3a8f304 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "cm_t335"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 1a841ce..1108e4b 100644 (file)
@@ -23,16 +23,3 @@ config SYS_CONFIG_NAME
        default "da850evm"
 
 endif
-
-if TARGET_HAWKBOARD
-
-config SYS_BOARD
-       default "da8xxevm"
-
-config SYS_VENDOR
-       default "davinci"
-
-config SYS_CONFIG_NAME
-       default "hawkboard"
-
-endif
index dd66f07..10c4e2f 100644 (file)
@@ -12,11 +12,3 @@ F:   include/configs/da850evm.h
 F:     configs/da850_am18xxevm_defconfig
 F:     configs/da850evm_defconfig
 F:     configs/da850evm_direct_nor_defconfig
-
-HAWKBOARD BOARD
-M:     Syed Mohammed Khasim <sm.khasim@gmail.com>
-M:     Sughosh Ganu <urwithsughosh@gmail.com>
-S:     Maintained
-F:     include/configs/hawkboard.h
-F:     configs/hawkboard_defconfig
-F:     configs/hawkboard_uart_defconfig
index d3acacc..4da509b 100644 (file)
@@ -9,4 +9,3 @@
 
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)   += da830evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)   += da850evm.o
-obj-$(CONFIG_MACH_DAVINCI_HAWK)                += hawkboard.o
diff --git a/board/davinci/da8xxevm/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard
deleted file mode 100644 (file)
index d6ae02e..0000000
+++ /dev/null
@@ -1,92 +0,0 @@
-Summary
-=======
-The README is for the boot procedure used for TI's OMAP-L138 based
-hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
-DDR SDRAM along with a host of other controllers.
-
-The hawkboard is booted in three stages. The initial bootloader which
-executes upon reset is the Rom Boot Loader(RBL) which sits in the
-internal ROM of the omap. The RBL initialises the memory and the nand
-controller, and copies the image stored at a predefined location(block
-1) of the nand flash. The image loaded by the RBL to the memory is the
-AIS signed spl image. This, in turns copies the u-boot binary from the
-nand flash to the memory and jumps to the u-boot entry point.
-
-AIS is an image format defined by TI for the images that are to be
-loaded to memory by the RBL. The image is divided into a series of
-sections and the image's entry point is specified. Each section comes
-with meta data like the target address the section is to be copied to
-and the size of the section, which is used by the RBL to load the
-image. At the end of the image the RBL jumps to the image entry
-point.
-
-The secondary stage bootloader(spl) which is loaded by the RBL then
-loads the u-boot from a predefined location in the nand to the memory
-and jumps to the u-boot entry point.
-
-The reason a secondary stage bootloader is used is because the ECC
-layout expected by the RBL is not the same as that used by
-u-boot/linux. This also implies that for flashing the spl image,we
-need to use the u-boot which uses the ECC layout expected by the
-RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
-
-
-Compilation
-===========
-Three images might be needed
-
-* spl - This is the secondary bootloader which boots the u-boot
-  binary.
-
-* u-boot binary - This is the image flashed to the nand and copied to
-  the memory by the spl.
-
-  Both the images get compiled with hawkboard_config, with the TOPDIR
-  containing the u-boot images, and the spl image under the spl
-  directory.
-
-  The spl image needs to be processed with the AISGen tool for
-  generating the AIS signed image to be flashed. Steps for generating
-  the AIS image are explained here[3].
-
-* u-boot for uart boot - This is same as the u-boot binary generated
-  above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
-  0xc1080000, as expected by the RBL.
-
-  hawkboard_uart_config
-
-
-Flashing the images to Nand
-===========================
-The spl AIS image needs to be flashed to the block 1 of the Nand
-flash, as that is the location the RBL expects the image[4]. For
-flashing the spl, boot over the u-boot specified in [1], and flash the
-image
-
-=> tftpboot 0xc0700000 <nand_spl_ais.bin>
-=> nand erase 0x20000 0x20000
-=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
-
-The u-boot binary is flashed at location 0xe0000(block 6) of the nand
-flash. The spl loader expects the u-boot at this location. For
-flashing the u-boot binary
-
-=> tftpboot 0xc0700000 u-boot.bin
-=> nand erase 0xe0000 0x40000
-=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
-
-
-Links
-=====
-
-[1]
- http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
-
-[2]
- http://elinux.org/Hawkboard#Booting_u-boot_over_UART
-
-[3]
- http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
-
-[4]
- http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
deleted file mode 100644 (file)
index 2b12b6c..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-#      PLL0CFG0        PLL0CFG1
-PLL0   0x00180001      0x00000205
-#      PLL1CFG0        PLL1CFG1        DRPYC1R         SDCR            SDTIMR1         SDTIMR2         SDRCR           CLK2XSRC
-DDR2   0x15010001      0x00000002      0x00000043      0x00134632      0x26492a09      0x7d13c722      0x00000249      0x00000000
diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c
deleted file mode 100644 (file)
index d5992a5..0000000
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
- *
- * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc.  <nsekhar@ti.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier:    GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/da8xx-usb.h>
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct pinmux_resource pinmuxes[] = {
-       PINMUX_ITEM(emac_pins_mii),
-       PINMUX_ITEM(emac_pins_mdio),
-       PINMUX_ITEM(emifa_pins_cs3),
-       PINMUX_ITEM(emifa_pins_cs4),
-       PINMUX_ITEM(emifa_pins_nand),
-       PINMUX_ITEM(uart2_pins_txrx),
-       PINMUX_ITEM(uart2_pins_rtscts),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
-       { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
-       { DAVINCI_LPSC_SPI1 },  /* Serial Flash */
-       { DAVINCI_LPSC_EMAC },  /* image download */
-       { DAVINCI_LPSC_UART2 }, /* console */
-       { DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-int board_init(void)
-{
-       /* arch number of the board */
-       gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
-
-       /* address of boot parameters */
-       gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-       return 0;
-}
-
-int board_early_init_f(void)
-{
-       /*
-        * Kick Registers need to be set to allow access to Pin Mux registers
-        */
-       writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
-       writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
-       /* set cfgchip3 to select mii */
-       writel(readl(&davinci_syscfg_regs->cfgchip3) &
-              ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
-
-       return 0;
-}
-
-int misc_init_r(void)
-{
-       char buf[32];
-
-       printf("ARM Clock : %s MHz\n",
-              strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
-
-       return 0;
-}
-
-int usb_phy_on(void)
-{
-       u32 timeout;
-       u32 cfgchip2;
-
-       cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-
-       cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
-                     CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ |
-                     CFGCHIP2_USB1PHYCLKMUX);
-       cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
-                   CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX |
-                   CFGCHIP2_USB1SUSPENDM;
-
-       writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-
-       /* wait until the usb phy pll locks */
-       timeout = DA8XX_USB_OTG_TIMEOUT;
-       while (timeout--)
-               if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
-                       return 1;
-
-       /* USB phy was not turned on */
-       return 0;
-}
-
-void usb_phy_off(void)
-{
-       u32 cfgchip2;
-
-       /*
-        * Power down the on-chip PHY.
-        */
-       cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-       cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM);
-       cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET;
-       writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-}
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
deleted file mode 100644 (file)
index 5c629db..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0xc1080000;
-
-       . = ALIGN(4);
-       .text      :
-       {
-         *(.vectors)
-         arch/arm/cpu/arm926ejs/start.o                (.text*)
-         arch/arm/cpu/arm926ejs/built-in.o             (.text*)
-         drivers/mtd/nand/built-in.o                   (.text*)
-
-         *(.text*)
-       }
-
-       . = ALIGN(4);
-       .rodata : { *(.rodata*) }
-
-       . = ALIGN(4);
-       .data : {
-               *(.data)
-       __datarel_start = .;
-               *(.data.rel)
-       __datarelrolocal_start = .;
-               *(.data.rel.ro.local)
-       __datarellocal_start = .;
-               *(.data.rel.local)
-       __datarelro_start = .;
-               *(.data.rel.ro)
-       }
-
-       . = ALIGN(4);
-       __image_copy_end = .;
-       __rel_dyn_start = .;
-       __rel_dyn_end = .;
-
-       __got_start = .;
-       . = ALIGN(4);
-       .got : { *(.got) }
-
-       __got_end = .;
-
-       .bss :
-       {
-               . = ALIGN(4);
-               __bss_start = .;
-               *(.bss*)
-               . = ALIGN(4);
-               __bss_end = .;
-       }
-
-       .end :
-       {
-               *(.__end)
-       }
-}
diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig
deleted file mode 100644 (file)
index 02c42cb..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_A320EVB
-
-config SYS_BOARD
-       default "a320evb"
-
-config SYS_VENDOR
-       default "faraday"
-
-config SYS_SOC
-       default "a320"
-
-config SYS_CONFIG_NAME
-       default "a320evb"
-
-endif
diff --git a/board/faraday/a320evb/MAINTAINERS b/board/faraday/a320evb/MAINTAINERS
deleted file mode 100644 (file)
index f13b015..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-A320EVB BOARD
-M:     Po-Yu Chuang <ratbert@faraday-tech.com>
-S:     Maintained
-F:     board/faraday/a320evb/
-F:     include/configs/a320evb.h
-F:     configs/a320evb_defconfig
diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile
deleted file mode 100644 (file)
index 518ce3f..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := a320evb.o
-obj-y  += lowlevel_init.o
diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c
deleted file mode 100644 (file)
index c42635b..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-#include <faraday/ftsmc020.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
-       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-       ftsmc020_init();        /* initialize Flash */
-       return 0;
-}
-
-int dram_init(void)
-{
-       unsigned long sdram_base = PHYS_SDRAM_1;
-       unsigned long expected_size = PHYS_SDRAM_1_SIZE;
-       unsigned long actual_size;
-
-       actual_size = get_ram_size((void *)sdram_base, expected_size);
-
-       gd->ram_size = actual_size;
-
-       if (expected_size != actual_size)
-               printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
-                               actual_size >> 20, expected_size >> 20);
-
-       return 0;
-}
-
-int board_eth_init(bd_t *bd)
-{
-       return ftmac100_initialize(bd);
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-       if (banknum == 0) {     /* non-CFI boot flash */
-               info->portwidth = FLASH_CFI_8BIT;
-               info->chipwidth = FLASH_CFI_BY8;
-               info->interface = FLASH_CFI_X8;
-               return 1;
-       } else
-               return 0;
-}
diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S
deleted file mode 100644 (file)
index d366260..0000000
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <asm/macro.h>
-#include <faraday/ftsdmc020.h>
-
-/*
- * parameters for the SDRAM controller
- */
-#define TP0_A          (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
-#define TP1_A          (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
-#define CR_A           (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
-#define B0_BSR_A       (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
-#define ACR_A          (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
-
-#define TP0_D          CONFIG_SYS_FTSDMC020_TP0
-#define TP1_D          CONFIG_SYS_FTSDMC020_TP1
-#define CR_D1          FTSDMC020_CR_IPREC
-#define CR_D2          FTSDMC020_CR_ISMR
-#define CR_D3          FTSDMC020_CR_IREF
-
-#define B0_BSR_D       (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
-                       FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
-#define ACR_D          FTSDMC020_ACR_TOC(0x18)
-
-/*
- * numeric 7 segment display
- */
-.macro led, num
-       write32 CONFIG_DEBUG_LED, \num
-.endm
-
-/*
- * Waiting for SDRAM to set up
- */
-.macro wait_sdram
-       ldr     r0, =CONFIG_FTSDMC020_BASE
-1:
-       ldr     r1, [r0, #FTSDMC020_OFFSET_CR]
-       cmp     r1, #0
-       bne     1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-       mov     r11, lr
-
-       led     0x0
-
-       bl      init_sdmc
-
-       led     0x1
-
-       /* everything is fine now */
-       mov     lr, r11
-       mov     pc, lr
-
-/*
- * memory initialization
- */
-init_sdmc:
-       led     0x10
-
-       /* set SDRAM register */
-
-       write32 TP0_A, TP0_D
-       led     0x11
-
-       write32 TP1_A, TP1_D
-       led     0x12
-
-       /* set to precharge */
-       write32 CR_A, CR_D1
-       led     0x13
-
-       wait_sdram
-       led     0x14
-
-       /* set mode register */
-       write32 CR_A, CR_D2
-       led     0x15
-
-       wait_sdram
-       led     0x16
-
-       /* set to refresh */
-       write32 CR_A, CR_D3
-       led     0x17
-
-       wait_sdram
-       led     0x18
-
-       write32 B0_BSR_A, B0_BSR_D
-       led     0x19
-
-       write32 ACR_A, ACR_D
-       led     0x1a
-
-       mov     pc, lr
index 3099a9e..750db85 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "pepper"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 2fe2ef1..9a8421e 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "am335x_igep0033"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 65094cf..bb98715 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "pcm051"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 2c5d3fc..006e864 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "s5p_goni"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 996fe3c..ea87166 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "smdkc100"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
index 6ecda80..2e9a2b3 100644 (file)
@@ -13,12 +13,12 @@ config SYS_CONFIG_NAME
        default "pengwyn"
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if !SPL_BUILD
+       default y
 
 config DM_SERIAL
-       default y if !SPL_BUILD
+       default y
 
 endif
diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig
deleted file mode 100644 (file)
index 6e9392e..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_JADECPU
-
-config SYS_BOARD
-       default "jadecpu"
-
-config SYS_VENDOR
-       default "syteco"
-
-config SYS_SOC
-       default "mb86r0x"
-
-config SYS_CONFIG_NAME
-       default "jadecpu"
-
-endif
diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS
deleted file mode 100644 (file)
index b53e7ca..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-JADECPU BOARD
-M:     Matthias Weisser <weisserm@arcor.de>
-S:     Maintained
-F:     board/syteco/jadecpu/
-F:     include/configs/jadecpu.h
-F:     configs/jadecpu_defconfig
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
deleted file mode 100644 (file)
index 7426436..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  += jadecpu.o
-obj-y  += lowlevel_init.o
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
deleted file mode 100644 (file)
index 6c60a41..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (c) 2010 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mb86r0x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-       struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
-                                       MB86R0x_CCNT_BASE;
-
-       /* We select mode 0 for group 2 and mode 1 for group 4 */
-       writel(0x00000010, &ccnt->cmux_md);
-
-       gd->flags = 0;
-       gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
-
-       icache_enable();
-       dcache_enable();
-
-       return 0;
-}
-
-static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
-                               unsigned long pwm_base)
-{
-       struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
-                                       MB86R0x_GPIO_BASE;
-       struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
-       const char *e;
-
-       writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
-
-       e = getenv(pwm_opts);
-       if (e != NULL) {
-               const char *s;
-               uint32_t freq, init;
-
-               freq = 0;
-               init = 0;
-
-               s = strchr(e, 'f');
-               if (s != NULL)
-                       freq = simple_strtol(s + 2, NULL, 0);
-
-               s = strchr(e, 'i');
-               if (s != NULL)
-                       init = simple_strtol(s + 2, NULL, 0);
-
-               if (freq > 0) {
-                       writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
-                               &pwm->bcr);
-                       writel(1002, &pwm->tpr);
-                       writel(1, &pwm->pr);
-                       writel(init * 10 + 1, &pwm->dr);
-                       writel(1, &pwm->cr);
-                       writel(1, &pwm->sr);
-               }
-       }
-}
-
-int board_late_init(void)
-{
-       struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
-                                       MB86R0x_GPIO_BASE;
-       uint32_t in_word;
-
-#ifdef CONFIG_VIDEO_MB86R0xGDC
-       /* Check if we have valid display settings and turn on power if so */
-       /* Display 0 */
-       if (getenv("gs_dsp_0_param") || getenv("videomode"))
-               setup_display_power((1 << 3), "gs_dsp_0_pwm",
-                                       MB86R0x_PWM0_BASE);
-
-       /* The corresponding GPIO is always an output */
-       writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
-
-       /* Display 1 */
-       if (getenv("gs_dsp_1_param") || getenv("videomode1"))
-               setup_display_power((1 << 4), "gs_dsp_1_pwm",
-                                       MB86R0x_PWM1_BASE);
-
-       /* The corresponding GPIO is always an output */
-       writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
-#endif /* CONFIG_VIDEO_MB86R0xGDC */
-
-       /* 5V enable */
-       writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
-       writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
-
-       /* We have special boot options if told by GPIOs */
-       in_word = readl(&gpio->gpdr1);
-
-       if ((in_word & 0xC0) == 0xC0) {
-               setenv("stdin", "serial");
-               setenv("stdout", "serial");
-               setenv("stderr", "serial");
-               setenv("preboot", "run gs_slow_boot");
-       } else if ((in_word & 0xC0) != 0) {
-               setenv("stdout", "vga");
-               setenv("preboot", "run gs_slow_boot");
-       } else {
-               setenv("stdin", "serial");
-               setenv("stdout", "serial");
-               setenv("stderr", "serial");
-               if (getenv("gs_devel")) {
-                       setenv("preboot", "run gs_slow_boot");
-               } else {
-                       setenv("preboot", "run gs_fast_boot");
-               }
-       }
-
-       return 0;
-}
-
-int misc_init_r(void)
-{
-       return 0;
-}
-
-/*
- * DRAM configuration
- */
-int dram_init(void)
-{
-       /* dram_init must store complete ramsize in gd->ram_size */
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
-                                       PHYS_SDRAM_SIZE);
-
-       return 0;
-}
-
-void dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-int board_eth_init(bd_t *bis)
-{
-       int rc = 0;
-#ifdef CONFIG_SMC911X
-       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-       return rc;
-}
diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S
deleted file mode 100644 (file)
index 9568cec..0000000
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/macro.h>
-#include <asm/arch/mb86r0x.h>
-#include <generated/asm-offsets.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-/*
- * Initialize Clock Reset Generator (CRG)
- */
-
-       ldr             r0, =MB86R0x_CRG_BASE
-
-       /* Not change the initial value that is set by external pin.*/
-WAIT_PLL:
-       ldr             r2, [r0, #CRG_CRPR]     /* Wait for PLLREADY */
-       tst             r2, #MB86R0x_CRG_CRPR_PLLRDY
-       beq             WAIT_PLL
-
-       /* Set clock gate control */
-       ldr             r1, =CONFIG_SYS_CRG_CRHA_INIT
-       str             r1, [r0, #CRG_CRHA]
-       ldr             r1, =CONFIG_SYS_CRG_CRPA_INIT
-       str             r1, [r0, #CRG_CRPA]
-       ldr             r1, =CONFIG_SYS_CRG_CRPB_INIT
-       str             r1, [r0, #CRG_CRPB]
-       ldr             r1, =CONFIG_SYS_CRG_CRHB_INIT
-       str             r1, [r0, #CRG_CRHB]
-       ldr             r1, =CONFIG_SYS_CRG_CRAM_INIT
-       str             r1, [r0, #CRG_CRAM]
-
-/*
- * Initialize External Bus Interface
- */
-       ldr             r0, =MB86R0x_MEMC_BASE
-
-       ldr             r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
-       str             r1, [r0, #MEMC_MCFMODE0]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
-       str             r1, [r0, #MEMC_MCFMODE2]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
-       str             r1, [r0, #MEMC_MCFMODE4]
-
-       ldr             r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
-       str             r1, [r0, #MEMC_MCFTIM0]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
-       str             r1, [r0, #MEMC_MCFTIM2]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
-       str             r1, [r0, #MEMC_MCFTIM4]
-
-       ldr             r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
-       str             r1, [r0, #MEMC_MCFAREA0]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
-       str             r1, [r0, #MEMC_MCFAREA2]
-       ldr             r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
-       str             r1, [r0, #MEMC_MCFAREA4]
-
-/*
- * Initialize DDR2 Controller
- */
-
-       /* Wait for PLL LOCK up time or more */
-       wait_timer      20
-
-       /*
-        * (2) Initialize DDRIF
-        */
-       ldr     r0, =MB86R0x_DDR2_BASE
-       ldr     r1, =CONFIG_SYS_DDR2_DRIMS_INIT
-       strh    r1, [r0, #DDR2_DRIMS]
-
-       /*
-        * (3) Wait for 20MCKPs(120nsec) or more
-        */
-       wait_timer      20
-
-       /*
-        * (4) IRESET/IUSRRST release
-        */
-       ldr     r0, =MB86R0x_CCNT_BASE
-       ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
-       str     r1, [r0, #CCNT_CDCRC]
-
-       /*
-        * (5) Wait for 20MCKPs(120nsec) or more
-        */
-       wait_timer      20
-
-       /*
-        * (6) IDLLRST release
-        */
-       ldr     r0, =MB86R0x_CCNT_BASE
-       ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
-       str     r1, [r0, #CCNT_CDCRC]
-
-       /*
-        * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
-        */
-       wait_timer      33536
-
-       /*
-        * (9) MCKE ON
-        */
-       ldr     r0, =MB86R0x_DDR2_BASE
-       ldr     r1, =CONFIG_SYS_DDR2_DRIC1_INIT
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_DRIC2_INIT
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =CONFIG_SYS_DDR2_DRCA_INIT
-       strh    r1, [r0, #DDR2_DRCA]
-       ldr     r1, =MB86R0x_DDR2_DRCI_INIT
-       strh    r1, [r0, #DDR2_DRIC]
-
-       /*
-        * (10) Initialize SDRAM
-        */
-
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       wait_timer      67                      /* 400ns wait */
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       wait_timer 200
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       wait_timer      18                      /* 105ns wait */
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       wait_timer      200                     /* MRS to OCD: 200clock */
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
-       strh    r1, [r0, #DDR2_DRIC1]
-       ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
-       strh    r1, [r0, #DDR2_DRIC2]
-       ldr     r1, =MB86R0x_DDR2_DRCI_CMD
-       strh    r1, [r0, #DDR2_DRIC]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRCM_INIT
-       strh    r1, [r0, #DDR2_DRCM]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRCST1_INIT
-       strh    r1, [r0, #DDR2_DRCST1]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRCST2_INIT
-       strh    r1, [r0, #DDR2_DRCST2]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRCR_INIT
-       strh    r1, [r0, #DDR2_DRCR]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRCF_INIT
-       strh    r1, [r0, #DDR2_DRCF]
-
-       ldr     r1, =CONFIG_SYS_DDR2_DRASR_INIT
-       strh    r1, [r0, #DDR2_DRASR]
-
-       /*
-        * (11) ODT setting
-        */
-       ldr     r1, =CONFIG_SYS_DDR2_DROBS_INIT
-       strh    r1, [r0, #DDR2_DROBS]
-       ldr     r1, =CONFIG_SYS_DDR2_DROABA_INIT
-       strh    r1, [r0, #DDR2_DROABA]
-       ldr     r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
-       strh    r1, [r0, #DDR2_DRIBSODT1]
-
-       /*
-        * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
-        */
-       ldr     r1, =CONFIG_SYS_DDR2_DROS_INIT
-       strh    r1, [r0, #DDR2_DROS]
-       ldr     r1, =MB86R0x_DDR2_DRCI_NORMAL
-       strh    r1, [r0, #DDR2_DRIC]
-
-       mov pc, lr
index a20e0c1..722f9d5 100644 (file)
@@ -39,18 +39,18 @@ config NOR_BOOT
          NOR for environment.
 
 config DM
-       default y if !SPL_BUILD
+       default y
 
 config DM_GPIO
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config DM_SERIAL
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config SYS_MALLOC_F
-       default y if DM && !SPL_BUILD
+       default y if DM
 
 config SYS_MALLOC_F_LEN
-       default 0x400 if DM && !SPL_BUILD
+       default 0x400 if DM
 
 endif
diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig
deleted file mode 100644 (file)
index 637f20e..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TNETV107X_EVM
-
-config SYS_BOARD
-       default "tnetv107xevm"
-
-config SYS_VENDOR
-       default "ti"
-
-config SYS_SOC
-       default "tnetv107x"
-
-config SYS_CONFIG_NAME
-       default "tnetv107x_evm"
-
-endif
diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS
deleted file mode 100644 (file)
index 8a92c6b..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-TNETV107XEVM BOARD
-#M:    Chan-Taek Park <c-park@ti.com>
-S:     Orphan (since 2014-06)
-F:     board/ti/tnetv107xevm/
-F:     include/configs/tnetv107x_evm.h
-F:     configs/tnetv107x_evm_defconfig
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile
deleted file mode 100644 (file)
index 0a6128f..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y          += sdb_board.o
diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk
deleted file mode 100644 (file)
index 51c2886..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x83FC0000
diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c
deleted file mode 100644 (file)
index a84ec84..0000000
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * TNETV107X-EVM: Board initialization
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <linux/mtd/nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
-       {                       /* CS0 */
-               .mode           = ASYNC_EMIF_MODE_NAND,
-               .wr_setup       = 5,
-               .wr_strobe      = 5,
-               .wr_hold        = 2,
-               .rd_setup       = 5,
-               .rd_strobe      = 5,
-               .rd_hold        = 2,
-               .turn_around    = 5,
-               .width          = ASYNC_EMIF_8,
-       },
-       {                       /* CS1 */
-               .mode           = ASYNC_EMIF_MODE_NOR,
-               .wr_setup       = 2,
-               .wr_strobe      = 27,
-               .wr_hold        = 4,
-               .rd_setup       = 2,
-               .rd_strobe      = 27,
-               .rd_hold        = 4,
-               .turn_around    = 2,
-               .width          = ASYNC_EMIF_PRESERVE,
-       },
-       {                       /* CS2 */
-               .mode           = ASYNC_EMIF_MODE_NOR,
-               .wr_setup       = 2,
-               .wr_strobe      = 27,
-               .wr_hold        = 4,
-               .rd_setup       = 2,
-               .rd_strobe      = 27,
-               .rd_hold        = 4,
-               .turn_around    = 2,
-               .width          = ASYNC_EMIF_PRESERVE,
-       },
-       {                       /* CS3 */
-               .mode           = ASYNC_EMIF_MODE_NOR,
-               .wr_setup       = 1,
-               .wr_strobe      = 90,
-               .wr_hold        = 3,
-               .rd_setup       = 1,
-               .rd_strobe      = 26,
-               .rd_hold        = 3,
-               .turn_around    = 1,
-               .width          = ASYNC_EMIF_8,
-       },
-};
-
-static struct pll_init_data pll_config[] = {
-       {
-               .pll                    = ETH_PLL,
-               .internal_osc           = 1,
-               .pll_freq               = 500000000,
-               .div_freq = {
-                       5000000, 50000000, 125000000, 250000000, 25000000,
-               },
-       },
-};
-
-static const short sdio1_pins[] = {
-       TNETV107X_PIN_SDIO1_CLK_1,      TNETV107X_PIN_SDIO1_CMD_1,
-       TNETV107X_PIN_SDIO1_DATA0_1,    TNETV107X_PIN_SDIO1_DATA1_1,
-       TNETV107X_PIN_SDIO1_DATA2_1,    TNETV107X_PIN_SDIO1_DATA3_1,
-       -1
-};
-
-static const short uart1_pins[] = {
-       TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
-};
-
-static const short ssp_pins[] = {
-       TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
-       TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
-       TNETV107X_PIN_SSP1_3, -1
-};
-
-int board_init(void)
-{
-#ifndef CONFIG_USE_IRQ
-       __raw_writel(0, INTC_GLB_EN);           /* Global disable       */
-       __raw_writel(0, INTC_HINT_EN);          /* Disable host ints    */
-       __raw_writel(0, INTC_EN_CLR0 + 0);      /* Clear enable         */
-       __raw_writel(0, INTC_EN_CLR0 + 4);      /* Clear enable         */
-       __raw_writel(0, INTC_EN_CLR0 + 8);      /* Clear enable         */
-#endif
-
-       gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
-       gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-       init_plls(ARRAY_SIZE(pll_config), pll_config);
-
-       init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
-
-       mux_select_pin(TNETV107X_PIN_ASR_CS3);
-       mux_select_pins(sdio1_pins);
-       mux_select_pins(uart1_pins);
-       mux_select_pins(ssp_pins);
-
-       return 0;
-}
-
-int dram_init(void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-       return 0;
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
-       davinci_nand_init(nand);
-
-       return 0;
-}
-#endif
index 2ca002d..f82bc88 100644 (file)
@@ -1,5 +1,4 @@
 menu "Command line interface"
-       depends on !SPL_BUILD
 
 config HUSH_PARSER
        bool "Use hush shell"
index 64c2951..6282919 100644 (file)
--- a/config.mk
+++ b/config.mk
@@ -24,6 +24,11 @@ VENDOR :=
 
 ARCH := $(CONFIG_SYS_ARCH:"%"=%)
 CPU := $(CONFIG_SYS_CPU:"%"=%)
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TEGRA
+CPU := arm720t
+endif
+endif
 BOARD := $(CONFIG_SYS_BOARD:"%"=%)
 ifneq ($(CONFIG_SYS_VENDOR),)
 VENDOR := $(CONFIG_SYS_VENDOR:"%"=%)
diff --git a/configs/a320evb_defconfig b/configs/a320evb_defconfig
deleted file mode 100644 (file)
index 5ebf5e6..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_A320EVB=y
diff --git a/configs/cm4008_defconfig b/configs/cm4008_defconfig
deleted file mode 100644 (file)
index 487589d..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_CM4008=y
diff --git a/configs/cm41xx_defconfig b/configs/cm41xx_defconfig
deleted file mode 100644 (file)
index 15e9362..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_CM41XX=y
diff --git a/configs/dkb_defconfig b/configs/dkb_defconfig
deleted file mode 100644 (file)
index 0be9578..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DKB=y
diff --git a/configs/hawkboard_defconfig b/configs/hawkboard_defconfig
deleted file mode 100644 (file)
index 4084f9c..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
diff --git a/configs/hawkboard_uart_defconfig b/configs/hawkboard_uart_defconfig
deleted file mode 100644 (file)
index d7eeae7..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
diff --git a/configs/jadecpu_defconfig b/configs/jadecpu_defconfig
deleted file mode 100644 (file)
index 4348e0e..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_JADECPU=y
index 86b4b15..fa8d291 100644 (file)
@@ -39,4 +39,4 @@ CONFIG_DM_I2C=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
index 242bcf9..12f0694 100644 (file)
@@ -39,4 +39,4 @@ CONFIG_DM_I2C=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
index 8e95f17..e66d166 100644 (file)
@@ -39,4 +39,4 @@ CONFIG_DM_I2C=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/tnetv107x_evm_defconfig b/configs/tnetv107x_evm_defconfig
deleted file mode 100644 (file)
index b0915d2..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TNETV107X_EVM=y
index 69dc459..288d17d 100644 (file)
@@ -17,109 +17,45 @@ source directory for a basic specification of Kconfig.
 Difference from Linux's Kconfig
 -------------------------------
 
-The biggest difference between Linux Kernel and U-Boot in terms of the
-configuration is that U-Boot has to configure multiple boot images per board:
-Normal, SPL, TPL.
-Kconfig functions need to be expanded for U-Boot to handle multiple images.
-The files scripts/kconfig/* were imported from Linux Kernel and adjusted
-for that purpose.
+Here are some worth-mentioning configuration targets.
 
-See below for how each configuration target works in U-Boot:
+- silentoldconfig
 
-- config, nconfig, menuconfig, xconfig, gconfig
+  This target updates .config, include/generated/autoconf.h and
+  include/configs/* as in Linux.  In U-Boot, it also does the followings
+  for the compatibility with the old configuration system:
 
-  These targets are used to configure Normal and create (or modify) the
-  .config file.  For SPL configuration, the configutation targets are prefixed
-  with "spl/", for example "make spl/config", "make spl/menuconfig", etc.
-  Those targets create or modify the spl/.config file.  Likewise, run
-  "make tpl/config", "make tpl/menuconfig", etc. for TPL.
+   * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
+     the SoC/CPU specific header directory
+   * create include/config.h
+   * create include/autoconf.mk
+   * create spl/include/autoconf.mk (SPL and TPL only)
+   * create tpl/include/autoconf.mk (TPL only)
 
-- silentoldconfig
+   If we could completely switch to Kconfig in a long run
+   (i.e. remove all the include/configs/*.h), those additional processings
+   above would be removed.
 
-  This target updates .config, include/generated/autoconf.h and
-  include/configs/*.  In U-Boot, the same thing is done for SPL, TPL,
-  if supported by the target board.  Depending on whether CONFIG_SPL and
-  CONFIG_TPL are defined, "make silentoldconfig" iterates three times at most
-  changing the work directory.
-
-  To sum up, "make silentoldconfig" possibly updates:
-  - .config, include/generated/autoconf.h, include/config/*
-  - spl/.config, spl/include/generated/autoconf.h, spl/include/config/*
-    (in case CONFIG_SPL=y)
-  - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/*
-    (in case CONFIG_TPL=y)
-
-- defconfig, <board>_defconfig
-
-  The target "<board>_defconfig" is used to create the .config based on the
-  file configs/<board>_defconfig.  The "defconfig" target is the same
-  except it checks for a file specified with KBUILD_DEFCONFIG environment.
-
-  Note:
-  The defconfig files are placed under the "configs" directory,
-  not "arch/$(ARCH)/configs".  This is because "ARCH" is not necessarily
-  given from the command line for the U-Boot configuration and build.
-
-  The defconfig file format in U-Boot has the special syntax; each line has
-  "<condition>:" prefix to show which image(s) the line is valid for.
-  For example,
-
-  CONFIG_FOO=100
-  S:CONFIG_FOO=200
-  T:CONFIG_FOO=300
-  ST:CONFIG_BAR=y
-  +S:CONFIG_BAZ=y
-  +T:CONFIG_QUX=y
-  +ST:CONFIG_QUUX=y
-
-  Here, the "<condition>:" prefix is one of:
-  None  - the line is valid only for Normal image
-  S:    - the line is valid only for SPL image
-  T:    - the line is valid only for TPL image
-  ST:   - the line is valid for SPL and TPL images
-  +S:   - the line is valid for Normal and SPL images
-  +T:   - the line is valid for Normal and TPL images
-  +ST:  - the line is valid for Normal, SPL and TPL images
-
-  So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file
-  has no "<condition>:" part and therefore has the same form as in Linux.
-  From the example defconfig shown above, three separete configuration sets
-  are generated and used for creating .config, spl/.config and tpl/.config.
-
-  - Input for the default configuration of Normal
-     CONFIG_FOO=100
-     CONFIG_BAZ=y
-     CONFIG_QUX=y
-     CONFIG_QUUX=y
-
-  - Input for the default configuration of SPL
-     CONFIG_FOO=200
-     CONFIG_BAR=y
-     CONFIG_BAZ=y
-     CONFIG_QUUX=y
-
-  - Input for the default configuration of TPL
-     CONFIG_FOO=300
-     CONFIG_BAR=y
-     CONFIG_QUX=y
-     CONFIG_QUUX=y
-
-- savedefconfig
-
-  This is the reverse operation of "make defconfig".  If neither CONFIG_SPL
-  nor CONFIG_TPL is defined in the .config file, it works like "savedefconfig"
-  in Linux Kernel: creates the minimal set of config based on the .config
-  and saves it into the "defconfig" file.  If CONFIG_SPL (and CONFIG_TPL) is
-  defined, the common lines among .config, spl/.config (and tpl/.config) are
-  coalesced together with "<condition:>" prefix for each line as shown above.
-  This file can be used as an input of "defconfig" target.
+- defconfig
+
+  In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
+
+- <board>_defconfig
+
+  Now it works as in Linux.
+  The prefixes such as "+S:" in *_defconfig are deprecated.
+  You can simply remove the prefixes.  Do not add them for new boards.
 
 - <board>_config
 
   This does not exist in Linux's Kconfig.
+  "make <board>_config" works the same as "make <board>_defconfig".
   Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
-  configuration.  It is still supported for backward compatibility and
-  its behavior is the same as "make <board>_defconfig".
+  configuration.  It is still supported for backward compatibility, so
+  we do not need to update the distro recipes.
+
+
+The other configuration targets work as in Linux Kernel.
 
 
 Migration steps to Kconfig
@@ -137,14 +73,10 @@ based configuration as follows:
 
 Configuration files for use in C sources
   - include/generated/autoconf.h     (generated by Kconfig for Normal)
-  - spl/include/generated/autoconf.h (generated by Kconfig for SPL)
-  - tpl/include/generated/autoconf.h (generated by Kconfig for TPL)
   - include/configs/<board>.h        (exists for all boards)
 
 Configuration file for use in makefiles
-  - include/config/auto.conf         (generated by Kconfig for Normal)
-  - spl/include/config/auto.conf     (generated by Kconfig for SPL)
-  - tpl/include/config/auto.conf     (generated by Kconfig for TPL)
+  - include/config/auto.conf         (generated by Kconfig)
   - include/autoconf.mk              (generated by the old config for Normal)
   - spl/include/autoconfig.mk        (generated by the old config for SPL)
   - tpl/include/autoconfig.mk        (generated by the old config for TPL)
@@ -215,8 +147,8 @@ TODO
   CONFIG_SYS_EXTRA_OPTIONS should not be used for new boards.
 
 - In the pre-Kconfig, a single board had multiple entries in the boards.cfg
-  file with differences in the option fields.  The correspoing defconfig files
-  were auto-generated when switching to Kconfig.  Now we have too many
+  file with differences in the option fields.  The corresponding defconfig
+  files were auto-generated when switching to Kconfig.  Now we have too many
   defconfig files compared with the number of the supported boards.  It is
   recommended to have only one defconfig per board and allow users to select
   the config options.
index 952ab87..cd8f4ae 100644 (file)
@@ -12,23 +12,30 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-icecube_5200     powerpc     mpc5xxx        -           -           Wolfgang Denk <wd@denx.de>
-Lite5200         powerpc     mpc5xxx        -           -
-cpci5200         powerpc     mpc5xxx        -           -           Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-mecp5200         powerpc     mpc5xxx        -           -           Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-pf5200           powerpc     mpc5xxx        -           -           Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-PM520            powerpc     mpc5xxx        -           -           Josef Wagner <Wagner@Microsys.de>
-Total5200        powerpc     mpc5xxx        -           -
-CATcenter        powerpc     ppc4xx         -           -
-PPChameleonEVB   powerpc     ppc4xx         -           -           Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-P2020DS          powerpc     mpc85xx        -           -
-P2020COME        powerpc     mpc85xx        -           -           Ira W. Snyder <iws@ovro.caltech.edu>
-P2020RDB         powerpc     mpc85xx        -           -           Poonam Aggrwal <poonam.aggrwal@freescale.com>
-P2010RDB         powerpc     mpc85xx        -           -
-P1020RDB         powerpc     mpc85xx        -           -
-P1011RDB         powerpc     mpc85xx        -           -
-MPC8360EMDS      powerpc     mpc83xx        -           -           Dave Liu <daveliu@freescale.com>
-MPC8360ERDK      powerpc     mpc83xx        -           -           Anton Vorontsov <avorontsov@ru.mvista.com>
+hawkboard        arm         arm926ejs      -           -           Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+tnetv107x        arm         arm1176        -           -           Chan-Taek Park <c-park@ti.com>
+a320evb          arm         arm920t        -           -           Po-Yu Chuang <ratbert@faraday-tech.com>
+cm4008           arm         arm920t        -           -           Greg Ungerer <greg.ungerer@opengear.com>
+cm41xx           arm         arm920t        -           -
+dkb              arm         arm926ejs      -           -           Lei Wen <leiwen@marvell.com>
+jadecpu          arm         arm926ejs      -           -           Matthias Weisser <weisserm@arcor.de>
+icecube_5200     powerpc     mpc5xxx        37b608a5    2015-01-23  Wolfgang Denk <wd@denx.de>
+Lite5200         powerpc     mpc5xxx        37b608a5    2015-01-23
+cpci5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+mecp5200         powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+pf5200           powerpc     mpc5xxx        37b608a5    2015-01-23  Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+PM520            powerpc     mpc5xxx        a258e732    2015-01-23  Josef Wagner <Wagner@Microsys.de>
+Total5200        powerpc     mpc5xxx        ad734f7d    2015-01-23
+CATcenter        powerpc     ppc4xx         5344cc1a    2015-01-23
+PPChameleonEVB   powerpc     ppc4xx         5344cc1a    2015-01-23  Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+P2020DS          powerpc     mpc85xx        168dcc6c    2015-01-23
+P2020COME        powerpc     mpc85xx        89123536    2015-01-23  Ira W. Snyder <iws@ovro.caltech.edu>
+P2020RDB         powerpc     mpc85xx        743d4815    2015-01-23  Poonam Aggrwal <poonam.aggrwal@freescale.com>
+P2010RDB         powerpc     mpc85xx        743d4815    2015-01-23
+P1020RDB         powerpc     mpc85xx        743d4815    2015-01-23
+P1011RDB         powerpc     mpc85xx        743d4815    2015-01-23
+MPC8360EMDS      powerpc     mpc83xx        8d1e3cb1    2015-01-23  Dave Liu <daveliu@freescale.com>
+MPC8360ERDK      powerpc     mpc83xx        8d1e3cb1    2015-01-23  Anton Vorontsov <avorontsov@ru.mvista.com>
 P3G4             powerpc     74xx_7xx       d928664f    2015-01-16  Wolfgang Denk <wd@denx.de>
 ZUMA             powerpc     74xx_7xx       d928664f    2015-01-16  Nye Liu <nyet@zumanetworks.com>
 ppmc7xx          powerpc     74xx_7xx       d928664f    2015-01-16
index f0d6110..75d182d 100644 (file)
@@ -1,6 +1,5 @@
 config DM
        bool "Enable Driver Model"
-       depends on !SPL_BUILD
        help
          This config option enables Driver Model. This brings in the core
          support, including scanning of platform data on start-up. If
@@ -22,31 +21,28 @@ config SPL_DM
 
 config DM_WARN
        bool "Enable warnings in driver model"
+       depends on DM
+       default y
        help
          The dm_warn() function can use up quite a bit of space for its
          strings. By default this is disabled for SPL builds to save space.
          This will cause dm_warn() to be compiled out - it will do nothing
          when called.
-       depends on DM
-       default y if !SPL_BUILD
-       default n if SPL_BUILD
 
 config DM_DEVICE_REMOVE
        bool "Support device removal"
+       depends on DM
+       default y
        help
          We can save some code space by dropping support for removing a
          device. This is not normally required in SPL, so by default this
          option is disabled for SPL.
-       depends on DM
-       default y if !SPL_BUILD
-       default n if SPL_BUILD
 
 config DM_STDIO
        bool "Support stdio registration"
+       depends on DM
+       default y
        help
          Normally serial drivers register with stdio so that they can be used
          as normal output devices. In SPL we don't normally use stdio, so
          we can omit this feature.
-       depends on DM
-       default y if !SPL_BUILD
-       default n if SPL_BUILD
index c242214..72825c3 100644 (file)
@@ -6,8 +6,6 @@ config SYS_NAND_SELF_INIT
          This option, if enabled, provides more flexible and linux-like
          NAND initialization process.
 
-if !SPL_BUILD
-
 config NAND_DENALI
        bool "Support Denali NAND controller"
        select SYS_NAND_SELF_INIT
@@ -34,9 +32,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES
          of OOB area before last ECC sector data starts.  This is potentially
          used to preserve the bad block marker in the OOB area.
 
-endif
-
-if SPL_BUILD
+if SPL
 
 config SPL_NAND_DENALI
        bool "Support Denali NAND controller for SPL"
index 6e1ccdb..b8b0803 100644 (file)
@@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GRETH) += greth.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
-obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c
deleted file mode 100644 (file)
index b4822e9..0000000
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * ks8695eth.c -- KS8695 ethernet driver
- *
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/****************************************************************************/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-/****************************************************************************/
-
-/*
- * Hardware register access to the KS8695 LAN ethernet port
- * (well, it is the 4 port switch really).
- */
-#define        ks8695_read(a)    *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
-#define        ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
-
-/****************************************************************************/
-
-/*
- * Define the descriptor in-memory data structures.
- */
-struct ks8695_txdesc {
-       uint32_t        owner;
-       uint32_t        ctrl;
-       uint32_t        addr;
-       uint32_t        next;
-};
-
-struct ks8695_rxdesc {
-       uint32_t        status;
-       uint32_t        ctrl;
-       uint32_t        addr;
-       uint32_t        next;
-};
-
-/****************************************************************************/
-
-/*
- * Allocate local data structures to use for receiving and sending
- * packets. Just to keep it all nice and simple.
- */
-
-#define        TXDESCS         4
-#define        RXDESCS         4
-#define        BUFSIZE         2048
-
-volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
-volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
-volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
-
-/****************************************************************************/
-
-/*
- *     Ideally we want to use the MAC address stored in flash.
- *     But we do some sanity checks in case they are not present
- *     first.
- */
-unsigned char eth_mac[] = {
-       0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
-};
-
-void ks8695_getmac(void)
-{
-       unsigned char *fp;
-       int i;
-
-       /* Check if flash MAC is valid */
-       fp = (unsigned char *) 0x0201c000;
-       for (i = 0; (i < 6); i++) {
-               if ((fp[i] != 0) && (fp[i] != 0xff))
-                       break;
-       }
-
-       /* If we found a valid looking MAC address then use it */
-       if (i < 6)
-               memcpy(&eth_mac[0], fp, 6);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
-{
-       int i;
-
-       debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
-
-       /* Reset the ethernet engines first */
-       ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
-       ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-
-       ks8695_getmac();
-
-       /* Set MAC address */
-       ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
-               (eth_mac[3] << 16) | (eth_mac[2] << 24)));
-       ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
-
-       /* Turn the 4 port switch on */
-       i = ks8695_read(KS8695_SWITCH_CTRL0);
-       ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
-       /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
-
-       /* Initialize descriptor rings */
-       for (i = 0; (i < TXDESCS); i++) {
-               ks8695_tx[i].owner = 0;
-               ks8695_tx[i].ctrl = 0;
-               ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
-               ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
-       }
-       ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
-       ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
-
-       for (i = 0; (i < RXDESCS); i++) {
-               ks8695_rx[i].status = 0x80000000;
-               ks8695_rx[i].ctrl = BUFSIZE - 4;
-               ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
-               ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
-       }
-       ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
-       ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
-
-       /* The KS8695 is pretty slow reseting the ethernets... */
-       udelay(2000000);
-
-       /* Enable the ethernet engine */
-       ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
-       ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
-       ks8695_write(KS8695_LAN_DMA_TX, 0x3);
-       ks8695_write(KS8695_LAN_DMA_RX, 0x71);
-       ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-
-       printf("KS8695 ETHERNET: %pM\n", eth_mac);
-       return 0;
-}
-
-/****************************************************************************/
-
-static void ks8695_eth_halt(struct eth_device *dev)
-{
-       debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
-
-       /* Reset the ethernet engines */
-       ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
-       ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_recv(struct eth_device *dev)
-{
-       volatile struct ks8695_rxdesc *dp;
-       int i, len = 0;
-
-       debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
-
-       for (i = 0; (i < RXDESCS); i++) {
-               dp= &ks8695_rx[i];
-               if ((dp->status & 0x80000000) == 0) {
-                       len = (dp->status & 0x7ff) - 4;
-                       NetReceive((void *) dp->addr, len);
-                       dp->status = 0x80000000;
-                       ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-                       break;
-               }
-       }
-
-       return len;
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
-{
-       volatile struct ks8695_txdesc *dp;
-       static int next = 0;
-
-       debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
-               packet, len);
-
-       dp = &ks8695_tx[next];
-       memcpy((void *) dp->addr, (void *) packet, len);
-
-       if (len < 64) {
-               memset((void *) (dp->addr + len), 0, 64-len);
-               len = 64;
-       }
-
-       dp->ctrl = len | 0xe0000000;
-       dp->owner = 0x80000000;
-
-       ks8695_write(KS8695_LAN_DMA_TX, 0x3);
-       ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
-
-       if (++next >= TXDESCS)
-               next = 0;
-
-       return 0;
-}
-
-/****************************************************************************/
-
-int ks8695_eth_initialize(void)
-{
-       struct eth_device *dev;
-
-       dev = malloc(sizeof(*dev));
-       if (dev == NULL)
-               return -1;
-       memset(dev, 0, sizeof(*dev));
-
-       dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
-       dev->init = ks8695_eth_init;
-       dev->halt = ks8695_eth_halt;
-       dev->send = ks8695_eth_send;
-       dev->recv = ks8695_eth_recv;
-       strcpy(dev->name, "ks8695eth");
-
-       eth_register(dev);
-       return 0;
-}
index 63b0cbf..b385852 100644 (file)
@@ -27,7 +27,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
-obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
 obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
index 95c992a..9f78492 100644 (file)
@@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize);
 serial_initfunc(imx_serial_initialize);
 serial_initfunc(iop480_serial_initialize);
 serial_initfunc(jz_serial_initialize);
-serial_initfunc(ks8695_serial_initialize);
 serial_initfunc(leon2_serial_initialize);
 serial_initfunc(leon3_serial_initialize);
 serial_initfunc(lh7a40x_serial_initialize);
@@ -220,7 +219,6 @@ void serial_initialize(void)
        imx_serial_initialize();
        iop480_serial_initialize();
        jz_serial_initialize();
-       ks8695_serial_initialize();
        leon2_serial_initialize();
        leon3_serial_initialize();
        lh7a40x_serial_initialize();
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
deleted file mode 100644 (file)
index 13adabd..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * serial.c -- KS8695 serial driver
- *
- * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#ifndef CONFIG_SERIAL1
-#error "Bad: you didn't configure serial ..."
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- *     Define the UART hardware register access structure.
- */
-struct ks8695uart {
-       unsigned int    RX;             /* 0x00 - Receive data (r) */
-       unsigned int    TX;             /* 0x04 - Transmit data (w) */
-       unsigned int    FCR;            /* 0x08 - Fifo Control (r/w) */
-       unsigned int    LCR;            /* 0x0c - Line Control (r/w) */
-       unsigned int    MCR;            /* 0x10 - Modem Control (r/w) */
-       unsigned int    LSR;            /* 0x14 - Line Status (r/w) */
-       unsigned int    MSR;            /* 0x18 - Modem Status (r/w) */
-       unsigned int    BD;             /* 0x1c - Baud Rate (r/w) */
-       unsigned int    SR;             /* 0x20 - Status (r/w) */
-};
-
-#define        KS8695_UART_ADDR        ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
-#define        KS8695_UART_CLK         25000000
-
-
-/*
- * Under some circumstances we want to be "quiet" and not issue any
- * serial output - though we want u-boot to otherwise work and behave
- * the same. By default be noisy.
- */
-int serial_console = 1;
-
-
-static void ks8695_serial_setbrg(void)
-{
-       volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
-       /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
-       uartp->BD = KS8695_UART_CLK / gd->baudrate;
-       uartp->LCR = KS8695_UART_LINEC_WLEN8;
-}
-
-static int ks8695_serial_init(void)
-{
-       serial_console = 1;
-       serial_setbrg();
-       return 0;
-}
-
-static void ks8695_serial_raw_putc(const char c)
-{
-       volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-       int i;
-
-       for (i = 0; (i < 0x100000); i++) {
-               if (uartp->LSR & KS8695_UART_LINES_TXFE)
-                       break;
-       }
-
-       uartp->TX = c;
-}
-
-static void ks8695_serial_putc(const char c)
-{
-       if (serial_console) {
-               ks8695_serial_raw_putc(c);
-               if (c == '\n')
-                       ks8695_serial_raw_putc('\r');
-       }
-}
-
-static int ks8695_serial_tstc(void)
-{
-       volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-       if (serial_console)
-               return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
-       return 0;
-}
-
-static int ks8695_serial_getc(void)
-{
-       volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
-       while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
-               ;
-       return (uartp->RX);
-}
-
-static struct serial_device ks8695_serial_drv = {
-       .name   = "ks8695_serial",
-       .start  = ks8695_serial_init,
-       .stop   = NULL,
-       .setbrg = ks8695_serial_setbrg,
-       .putc   = ks8695_serial_putc,
-       .puts   = default_serial_puts,
-       .getc   = ks8695_serial_getc,
-       .tstc   = ks8695_serial_tstc,
-};
-
-void ks8695_serial_initialize(void)
-{
-       serial_register(&ks8695_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-       return &ks8695_serial_drv;
-}
index af2d47b..22a316b 100644 (file)
@@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
-obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c
deleted file mode 100644 (file)
index bb7a749..0000000
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
- * controller.
- */
-
-#include <common.h>
-
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * 4MB (at the end of system RAM)
- */
-#define VIDEO_MEM_SIZE         0x400000
-
-#define FB_SYNC_CLK_INV                (1<<16) /* pixel clock inverted */
-
-/*
- * Graphic Device
- */
-static GraphicDevice mb86r0x;
-
-static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
-                       u32 *videomem)
-{
-       struct ctfb_res_modes var_mode;
-       u32 dcm1, dcm2, dcm3;
-       u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
-       u8 hsw, vsw;
-       u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
-       u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
-       unsigned long div;
-       int bpp;
-
-       bpp = video_get_params(&var_mode, modestr);
-
-       if (bpp == 0) {
-               var_mode.xres = 640;
-               var_mode.yres = 480;
-               var_mode.pixclock = 39721;      /* 25MHz */
-               var_mode.left_margin = 48;
-               var_mode.right_margin = 16;
-               var_mode.upper_margin = 33;
-               var_mode.lower_margin = 10;
-               var_mode.hsync_len = 96;
-               var_mode.vsync_len = 2;
-               var_mode.sync = 0;
-               var_mode.vmode = 0;
-               bpp = 15;
-       }
-
-       /* Fill memory with white */
-       memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
-
-       mb86r0x.winSizeX = var_mode.xres;
-       mb86r0x.winSizeY = var_mode.yres;
-
-       /* LCD base clock is ~ 660MHZ. We do calculations in kHz */
-       div = 660000 / (1000000000L / var_mode.pixclock);
-       if (div > 64)
-               div = 64;
-       if (0 == div)
-               div = 1;
-
-       dcm1 = (div - 1) << 8;
-       dcm2 = 0x00000000;
-       if (var_mode.sync & FB_SYNC_CLK_INV)
-               dcm3 = 0x00000100;
-       else
-               dcm3 = 0x00000000;
-
-       htp = var_mode.left_margin + var_mode.xres +
-               var_mode.hsync_len + var_mode.right_margin;
-       hdp = var_mode.xres;
-       hdb = var_mode.xres;
-       hsp = var_mode.xres + var_mode.right_margin;
-       hsw = var_mode.hsync_len;
-
-       vsw = var_mode.vsync_len;
-       vtr = var_mode.upper_margin + var_mode.yres +
-               var_mode.vsync_len + var_mode.lower_margin;
-       vsp = var_mode.yres + var_mode.lower_margin;
-       vdp = var_mode.yres;
-
-       l2m =   ((var_mode.yres - 1) << (0)) |
-               (((var_mode.xres * 2) / 64) << (16)) |
-               ((1) << (31));
-
-       l2em = (1 << 0) | (1 << 1);
-
-       l2oa0 = mb86r0x.frameAdrs;
-       l2da0 = mb86r0x.frameAdrs;
-       l2oa1 = mb86r0x.frameAdrs;
-       l2da1 = mb86r0x.frameAdrs;
-       l2dx = 0;
-       l2dy = 0;
-       l2wx = 0;
-       l2wy = 0;
-       l2ww = var_mode.xres;
-       l2wh = var_mode.yres - 1;
-
-       writel(dcm1, &dsp->dcm1);
-       writel(dcm2, &dsp->dcm2);
-       writel(dcm3, &dsp->dcm3);
-
-       writew(htp, &dsp->htp);
-       writew(hdp, &dsp->hdp);
-       writew(hdb, &dsp->hdb);
-       writew(hsp, &dsp->hsp);
-       writeb(hsw, &dsp->hsw);
-
-       writeb(vsw, &dsp->vsw);
-       writew(vtr, &dsp->vtr);
-       writew(vsp, &dsp->vsp);
-       writew(vdp, &dsp->vdp);
-
-       writel(l2m, &dsp->l2m);
-       writel(l2em, &dsp->l2em);
-       writel(l2oa0, &dsp->l2oa0);
-       writel(l2da0, &dsp->l2da0);
-       writel(l2oa1, &dsp->l2oa1);
-       writel(l2da1, &dsp->l2da1);
-       writew(l2dx, &dsp->l2dx);
-       writew(l2dy, &dsp->l2dy);
-       writew(l2wx, &dsp->l2wx);
-       writew(l2wy, &dsp->l2wy);
-       writew(l2ww, &dsp->l2ww);
-       writew(l2wh, &dsp->l2wh);
-
-       writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
-}
-
-void *video_hw_init(void)
-{
-       struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
-       GraphicDevice *pGD = &mb86r0x;
-       char *s;
-       u32 *vid;
-
-       memset(pGD, 0, sizeof(GraphicDevice));
-
-       pGD->gdfIndex = GDF_15BIT_555RGB;
-       pGD->gdfBytesPP = 2;
-       pGD->memSize = VIDEO_MEM_SIZE;
-       pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
-
-       vid = (u32 *)pGD->frameAdrs;
-
-       s = getenv("videomode");
-       if (s != NULL)
-               dsp_init(&gdc->dsp0, s, vid);
-
-       s = getenv("videomode1");
-       if (s != NULL)
-               dsp_init(&gdc->dsp1, s, vid);
-
-       return pGD;
-}
index 1dc0f5a..482a4bd 100644 (file)
@@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
 ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
 obj-y += imx_watchdog.o
 endif
-obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
 obj-$(CONFIG_S5P)               += s5p_wdt.o
 obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
 obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c
deleted file mode 100644 (file)
index 3d3f366..0000000
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV                0xFFFE0001
-
-struct wdt_regs {
-       u32 kick_lock;
-#define KICK_LOCK_1    0x5555
-#define KICK_LOCK_2    0xaaaa
-       u32 kick;
-
-       u32 change_lock;
-#define CHANGE_LOCK_1  0x6666
-#define CHANGE_LOCK_2  0xbbbb
-       u32 change;
-
-       u32 disable_lock;
-#define DISABLE_LOCK_1 0x7777
-#define DISABLE_LOCK_2 0xcccc
-#define DISABLE_LOCK_3 0xdddd
-       u32 disable;
-
-       u32 prescale_lock;
-#define PRESCALE_LOCK_1        0x5a5a
-#define PRESCALE_LOCK_2        0xa5a5
-       u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg)      __raw_readl(&regs->reg)
-#define wdt_reg_write(reg, val)        __raw_writel((val), &regs->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
-       wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
-       if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
-               return -1;
-
-       wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
-       if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
-               return -1;
-
-       wdt_reg_write(prescale, prescale_value);
-
-       return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
-       wdt_reg_write(change_lock, CHANGE_LOCK_1);
-       if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
-               return -1;
-
-       wdt_reg_write(change_lock, CHANGE_LOCK_2);
-       if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
-               return -1;
-
-       wdt_reg_write(change, initial_timer_value);
-
-       return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
-       wdt_reg_write(disable_lock, DISABLE_LOCK_1);
-       if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
-               return -1;
-
-       wdt_reg_write(disable_lock, DISABLE_LOCK_2);
- &nb