u-boot.git
4 years agotools/env: ensure environment starts at erase block boundary
Andreas Fenkart [Thu, 11 Aug 2016 19:39:17 +0000 (21:39 +0200)]
tools/env: ensure environment starts at erase block boundary

56086921 added support for unaligned environments access.
U-boot itself does not support this:
- env_nand.c fails when using an unaligned offset. It produces an
  error in nand_erase_opts{drivers/mtd/nand/nand_util.c}
- in env_sf/env_flash the unused space at the end is preserved, but
  not in the beginning. block alignment is assumed
- env_sata/env_mmc aligns offset/length to the block size of the
  underlying device. data is silently redirected to the beginning of
  a block

There is seems no use case for unaligned environment. If there is
some useful data at the beginning of the the block (e.g. end of u-boot)
that would be very unsafe. If the redundant environments are hosted by
the same erase block then that invalidates the idea of double buffering.
It might be that unaligned access was allowed in the past, and that
people with legacy u-boot are trapped. But at the time of 56086921
it wasn't supported and due to reasons above I guess it was never
introduced.
I prefer to remove that (unused) feature in favor of simplicity

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
4 years agoxtensa: add support for the 'xtfpga' evaluation board
Chris Zankel [Wed, 10 Aug 2016 15:36:48 +0000 (18:36 +0300)]
xtensa: add support for the 'xtfpga' evaluation board

The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.

 - Avnet Xilinx LX60
 - Avnet Xilinx LX110
 - Avnet Xilinx LX200
 - Xilinx ML605
 - Xilinx KC705

These boards share the same components (open-ethernet, ns16550 serial,
lcd display, flash, etc.).

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the de212 processor
Max Filippov [Wed, 10 Aug 2016 15:36:47 +0000 (18:36 +0300)]
xtensa: add core information for the de212 processor

DE212 is a general purpose xtensa processor without full MMU.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the dc233c processor
Max Filippov [Wed, 10 Aug 2016 15:36:46 +0000 (18:36 +0300)]
xtensa: add core information for the dc233c processor

DC233C is an xtensa processor with full MMUv3 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the dc232b processor
Chris Zankel [Wed, 10 Aug 2016 15:36:45 +0000 (18:36 +0300)]
xtensa: add core information for the dc232b processor

DC232B is an xtensa processor with full MMUv2 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add support for the xtensa processor architecture [2/2]
Chris Zankel [Wed, 10 Aug 2016 15:36:44 +0000 (18:36 +0300)]
xtensa: add support for the xtensa processor architecture [2/2]

The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add support for the xtensa processor architecture [1/2]
Chris Zankel [Wed, 10 Aug 2016 15:36:43 +0000 (18:36 +0300)]
xtensa: add support for the xtensa processor architecture [1/2]

The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.

This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agovexpress: Check TC2 firmware support before defaulting to nonsec booting
Jon Medhurst \(Tixy\) [Thu, 23 Jun 2016 12:37:32 +0000 (13:37 +0100)]
vexpress: Check TC2 firmware support before defaulting to nonsec booting

The firmware on TC2 needs to be configured appropriately before booting
in nonsec mode will work as expected, so test for this and fall back to
sec mode if required.

Signed-off-by: Jon Medhurst <tixy@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-atmel
Tom Rini [Mon, 15 Aug 2016 21:31:23 +0000 (17:31 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel

4 years agommc: atmel_sdhci: Convert to the driver model support
Wenyou Yang [Wed, 10 Aug 2016 02:51:05 +0000 (10:51 +0800)]
mmc: atmel_sdhci: Convert to the driver model support

Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agodm: atmel: Add driver model support for the ehci driver
Wenyou Yang [Fri, 5 Aug 2016 00:57:35 +0000 (08:57 +0800)]
dm: atmel: Add driver model support for the ehci driver

Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agoARM: at91/dt: Add device tree for SAMA5D2 Xplained
Wenyou Yang [Mon, 25 Jul 2016 09:46:17 +0000 (17:46 +0800)]
ARM: at91/dt: Add device tree for SAMA5D2 Xplained

Add device tree for SAMA5D2 Xplained board.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
4 years agoatmel: Bring in at91 pio4 device tree file and bindings
Wenyou Yang [Wed, 20 Jul 2016 09:16:28 +0000 (17:16 +0800)]
atmel: Bring in at91 pio4 device tree file and bindings

Bring in required device tree file and bindings from Linux.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agopinctrl: at91-pio4: Add pinctrl driver
Wenyou Yang [Wed, 20 Jul 2016 09:16:27 +0000 (17:16 +0800)]
pinctrl: at91-pio4: Add pinctrl driver

AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
4 years agogpio: atmel_pio4: Rework to support DM & DT
Wenyou Yang [Wed, 20 Jul 2016 09:16:26 +0000 (17:16 +0800)]
gpio: atmel_pio4: Rework to support DM & DT

Rework the driver to support driver model and device tree, and
support to regard the pio4 pinctrl device as a child of
atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agogpio: atmel_pio4: Move PIO4 definitions to head file
Wenyou Yang [Wed, 20 Jul 2016 09:16:25 +0000 (17:16 +0800)]
gpio: atmel_pio4: Move PIO4 definitions to head file

In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoclk.h: inline clk_get_by_name()
Andreas Bießmann [Mon, 15 Aug 2016 19:04:41 +0000 (21:04 +0200)]
clk.h: inline clk_get_by_name()

Fix compile warning for non OF_CONTROL builds:

---8<---
In file included from /Volumes/devel/u-boot/drivers/gpio/atmel_pio4.c:10:0:
/Volumes/devel/u-boot/include/clk.h:107:12: warning: 'clk_get_by_name' defined but not used [-Wunused-function]
--->8---

Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Mon, 15 Aug 2016 20:38:39 +0000 (16:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net

4 years agonet: mii: Clean up legacy glue that is not used
Joe Hershberger [Mon, 8 Aug 2016 16:28:41 +0000 (11:28 -0500)]
net: mii: Clean up legacy glue that is not used

The cleanup of the legacy mii registration API that's no longer used now
that the drivers have been converted to use the (more) modern API.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Changes not made by spatch
Joe Hershberger [Mon, 8 Aug 2016 16:28:39 +0000 (11:28 -0500)]
net: mii: Changes not made by spatch

If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.

Make those changes manually.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
For the 4xx related files:
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Fix changes made by spatch
Joe Hershberger [Mon, 8 Aug 2016 16:28:40 +0000 (11:28 -0500)]
net: mii: Fix changes made by spatch

Some of the changes were a bit too complex.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Use spatch to update miiphy_register
Joe Hershberger [Mon, 8 Aug 2016 16:28:38 +0000 (11:28 -0500)]
net: mii: Use spatch to update miiphy_register

Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoscripts: Add a cocci patch for miiphy_register
Joe Hershberger [Mon, 8 Aug 2016 16:28:37 +0000 (11:28 -0500)]
scripts: Add a cocci patch for miiphy_register

Many Ethernet drivers still use the legacy miiphy API to register their
mdio interface for access to the mdio commands.

This semantic patch will convert the drivers from the legacy adapter API
to the more modern alloc/register API.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agoclk: at91: Add clock driver
Wenyou Yang [Wed, 20 Jul 2016 09:55:12 +0000 (17:55 +0800)]
clk: at91: Add clock driver

The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotpm: atmel_twi: Make compatible with DM I2C busses
mario.six@gdsys.cc [Mon, 18 Jul 2016 11:47:45 +0000 (13:47 +0200)]
tpm: atmel_twi: Make compatible with DM I2C busses

Commit 302c5db ("dm: tpm: Add Driver Model support for tpm_atmel_twi
driver") converted the Atmel TWI TPM driver itself to driver model, but
kept the legacy-style i2c_write/i2c_read calls.

Commit 3e7d940 ("dm: tpm: Every TPM drivers should depends on DM_TPM")
then made DM_I2C a dependency of the driver, effectively forcing users
to turn on CONFIG_DM_I2C_COMPAT to get it to work.

This patch adds the necessary dm_i2c_write/dm_i2c_read calls to make the
driver compatible with DM, but also keeps the legacy calls in ifdefs, so
that the driver is now compatible with both DM and non-DM setups.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
4 years agoi2c: atmel: DT binding for i2c driver
Songjun Wu [Mon, 20 Jun 2016 05:22:39 +0000 (13:22 +0800)]
i2c: atmel: DT binding for i2c driver

DT binding documentation for atmel i2c driver.

Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: atmel: add i2c driver
Songjun Wu [Mon, 20 Jun 2016 05:22:38 +0000 (13:22 +0800)]
i2c: atmel: add i2c driver

Add i2c driver.

Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
4 years agonet/ethoc: implement MDIO bus and support phylib
Max Filippov [Fri, 5 Aug 2016 15:26:21 +0000 (18:26 +0300)]
net/ethoc: implement MDIO bus and support phylib

Implement MDIO bus read/write functions, initialize the bus and scan for
the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: support private memory configurations
Max Filippov [Fri, 5 Aug 2016 15:26:20 +0000 (18:26 +0300)]
net/ethoc: support private memory configurations

The ethoc device can be configured to have a private memory region
instead of having access to the main memory. In that case egress packets
must be copied into that memory for transmission and pointers to that
memory need to be passed to net_process_received_packet or returned from
the recv callback.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: don't mix virtual and physical addresses
Max Filippov [Fri, 5 Aug 2016 15:26:19 +0000 (18:26 +0300)]
net/ethoc: don't mix virtual and physical addresses

Addresses used in buffer descriptors and passed in platform data or
device tree are physical. Addresses used by CPU to access packet data
and registers are virtual. Don't mix these addresses and use virt_to_phys
for translation.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: support device tree
Max Filippov [Fri, 5 Aug 2016 15:26:18 +0000 (18:26 +0300)]
net/ethoc: support device tree

Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
device configuration from the device tree.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: add CONFIG_DM_ETH support
Max Filippov [Fri, 5 Aug 2016 15:26:17 +0000 (18:26 +0300)]
net/ethoc: add CONFIG_DM_ETH support

Extract reusable parts from ethoc_init, ethoc_set_mac_address,
ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
Add U_BOOT_DRIVER, eth_ops structure and implement required methods.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: use priv instead of dev internally
Max Filippov [Fri, 5 Aug 2016 15:26:16 +0000 (18:26 +0300)]
net/ethoc: use priv instead of dev internally

Don't use physical base address of registers directly, ioremap it first.
Save pointer in private struct ethoc and use that struct in all internal
functions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: add Kconfig entry for the driver
Max Filippov [Fri, 5 Aug 2016 15:26:15 +0000 (18:26 +0300)]
net/ethoc: add Kconfig entry for the driver

Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
only board configuration that uses it and put it into that board's
defconfig.

Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: e1000: Fix the build with driver model and SPI EEPROM
Alban Bedel [Wed, 3 Aug 2016 09:31:03 +0000 (11:31 +0200)]
net: e1000: Fix the build with driver model and SPI EEPROM

When adding support for the driver model the SPI EEPROM feature had
been ignored. Fix the build with both CONFIG_DM_ETH and
CONFIG_E1000_SPI enabled.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: smsc95xx: Use correct get_unaligned functions
Chris Packham [Tue, 12 Jul 2016 21:52:36 +0000 (09:52 +1200)]
net: smsc95xx: Use correct get_unaligned functions

The __get_unaligned_le* functions may not be declared on all platforms.
Instead, get_unaligned_le* should be used. On many platforms both of
these are the same function.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: macb: Fix build error for CONFIG_DM_ETH enabled
Wenyou Yang [Tue, 17 May 2016 05:11:35 +0000 (13:11 +0800)]
net: macb: Fix build error for CONFIG_DM_ETH enabled

Use the right phy_connect() prototype for CONFIGF_DM_ETH.
Support to get the phy interface from dt and set GMAC_UR.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agoARM: tegra: set vdd_core for Jetson TK1
Bibek Basu [Thu, 11 Aug 2016 22:28:28 +0000 (16:28 -0600)]
ARM: tegra: set vdd_core for Jetson TK1

Program vdd_core for Jetson TK1 to 1V, which is the max safe voltage for
ultra low temperature operations. vdd_cpu and vdd_gpu are already at 1V.

Signed-off-by: Bibek Basu <bbasu@nvidia.com>
(swarren: fixed comments to better match the code)
(swarren: moved board ifdef around data in header, made code generic)
(swarren: fixed typos in commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: reduce CSITE clock from 204M to 136M
Bryan Wu [Thu, 11 Aug 2016 22:28:27 +0000 (16:28 -0600)]
ARM: tegra: reduce CSITE clock from 204M to 136M

The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust the
rate to 136MHz to avoid the warning and stay in spec.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, re-wrote commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: fix trimslice environment location
Stephen Warren [Mon, 8 Aug 2016 19:56:35 +0000 (13:56 -0600)]
ARM: tegra: fix trimslice environment location

Trimslice currently stores its environment at 512KiB into the SPI flash
chip. The U-Boot binary has grown such that the size of the boot image
(which includes the Tegra BCT, padding, and the U-Boot binary) is slightly
larger than 512K now. Consequently, writing the boot image to flash
corrupts the saved environment, and equally, writing to or erasing the
environment will corrupt the bootloader, which in turn will cause the
Tegra boot ROM to enter recovery mode during boot, making it look as if
the system is non-operational. Note that tegra-uboot-flasher writes to
the environment during the flashing process.

Solve this by moving the environment as high as possible in flash. This
will allow the U-Boot binary to roughly double in size before this problem
is hit again, at which point there's nothing we can do anyway since the
binary won't fit into flash.

99% of other Tegra boards store the environment in eMMC and use a negative
value for CONFIG_ENV_OFFSET, which already automatically places the
environment as near the end of boot flash as possible. The 1 remaining
board hard-codes CONFIG_ENV_OFFSET to 2MiB, which allows for plenty more
bloat.

Reported-by: Stephen L Arnold <nerdboy@gentoo.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: move ft_system_setup()
Stephen Warren [Mon, 8 Aug 2016 16:38:34 +0000 (10:38 -0600)]
ARM: tegra: move ft_system_setup()

Currently, ft_system_setup() is implemented by board*.c, which are a bit
of a dumping ground for a bunch of unrelated functionality, and separate
versions exist for pre-Tegra186 and Tegra186. Move the implementation into
a separate file to separate functionality, and allow sharing.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable PCIe controller on p2771-0000
Stephen Warren [Fri, 29 Jul 2016 19:15:06 +0000 (13:15 -0600)]
ARM: tegra: enable PCIe controller on p2771-0000

p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI
connector (which may run at x2 electrically, depending on the board
version and configuration) and a x1 connection to the M.2 slot (which may
not be active, depending on the board version and configuration). This
change enables those.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable SD card on p2771-0000
Stephen Warren [Fri, 29 Jul 2016 19:15:05 +0000 (13:15 -0600)]
ARM: tegra: enable SD card on p2771-0000

Now that clock and reset drivers exist for Tegra186, we can enable the SD
card controller. Now that a BPMP I2C driver exists for Tegra186, we can
communicate with the PMIC to enable power to the SD card. Hook up the DT
content and board code required to make the SD card work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable I2C buses for P2771-0000
Bryan Wu [Wed, 27 Jul 2016 21:48:22 +0000 (15:48 -0600)]
ARM: tegra: enable I2C buses for P2771-0000

Enable I2C devices in DT and enable building tegra_i2c.c driver.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, commit msg rework, fixed DT node sort order)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoi2c: tegra: add standardized clk/reset API support
Bryan Wu [Fri, 5 Aug 2016 22:10:35 +0000 (16:10 -0600)]
i2c: tegra: add standardized clk/reset API support

clk/reset API was tested on T186 platform and previous chip like
T210/T124 will still use the old APIs.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, simplified some ifdefs, removed indent level inside an ifdef)
(swarren, added comment about the ifdefs)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agopci: tegra: port to standard clock/reset/pwr domain APIs
Stephen Warren [Fri, 5 Aug 2016 22:10:34 +0000 (16:10 -0600)]
pci: tegra: port to standard clock/reset/pwr domain APIs

Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agommc: tegra: port to standard clock/reset APIs
Stephen Warren [Fri, 5 Aug 2016 22:10:33 +0000 (16:10 -0600)]
mmc: tegra: port to standard clock/reset APIs

Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoi2c: add Tegra186 BPMP driver
Stephen Warren [Mon, 8 Aug 2016 17:28:27 +0000 (11:28 -0600)]
i2c: add Tegra186 BPMP driver

On Tegra186, some I2C controllers are directly controlled by the main CPU,
whereas others are controlled by the BPMP, and can only be accessed by the
main CPU via IPC requests to the BPMP. This driver covers the latter case.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agopower domain: add Tegra186 driver
Stephen Warren [Mon, 8 Aug 2016 17:28:26 +0000 (11:28 -0600)]
power domain: add Tegra186 driver

In Tegra186, SoC power domains are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoreset: add Tegra186 reset driver
Stephen Warren [Mon, 8 Aug 2016 17:28:25 +0000 (11:28 -0600)]
reset: add Tegra186 reset driver

In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoclock: add Tegra186 clock driver
Stephen Warren [Mon, 8 Aug 2016 17:28:24 +0000 (11:28 -0600)]
clock: add Tegra186 clock driver

In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agomisc: add Tegra BPMP driver
Stephen Warren [Mon, 8 Aug 2016 15:41:34 +0000 (09:41 -0600)]
misc: add Tegra BPMP driver

The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 12 Aug 2016 20:00:50 +0000 (16:00 -0400)]
Merge git://git.denx.de/u-boot-dm

4 years agomisc: add "call" uclass op
Stephen Warren [Mon, 8 Aug 2016 15:41:33 +0000 (09:41 -0600)]
misc: add "call" uclass op

The call op requests that the callee pass a message to the underlying HW
or device, wait for a response, and then pass back the response error code
and message to the callee. It is useful for drivers that represent some
kind of messaging or IPC channel to a remote device.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agopower: pmic: act8846: add missing newline to debug statements
John Keeping [Sun, 7 Aug 2016 11:55:40 +0000 (12:55 +0100)]
power: pmic: act8846: add missing newline to debug statements

Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agopower: regulator: act8846: fix reading values
John Keeping [Sun, 7 Aug 2016 11:55:39 +0000 (12:55 +0100)]
power: regulator: act8846: fix reading values

The voltage and control registers need to be looked up from the value in
driver_data.  Adjust the get_value and get_enable functions to match the
corresponding set_* functions.

Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agofdt: allow fdtdec_get_addr_size_*() to translate addresses
Stephen Warren [Fri, 5 Aug 2016 15:47:51 +0000 (09:47 -0600)]
fdt: allow fdtdec_get_addr_size_*() to translate addresses

Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agofdt_support: fdt_translate_address() blob const correctness
Stephen Warren [Fri, 5 Aug 2016 15:47:50 +0000 (09:47 -0600)]
fdt_support: fdt_translate_address() blob const correctness

The next patch will call fdt_translate_address() from somewhere with a
"const void *blob" rather than a "void *blob", so fdt_translate_address()
must accept a const pointer too. Constify the minimum number of function
parameters to achieve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agokconfig: use bool instead of boolean for type definition attributes
Masahiro Yamada [Fri, 12 Aug 2016 01:26:50 +0000 (10:26 +0900)]
kconfig: use bool instead of boolean for type definition attributes

Linux stopped the use of keyword 'boolean' in Kconfig.

Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agodefconfig: am43xx_evm: enable eth driver model
Mugunthan V N [Thu, 11 Aug 2016 08:57:04 +0000 (14:27 +0530)]
defconfig: am43xx_evm: enable eth driver model

Enable eth driver model for am43xx_evm as cpsw supports
driver model.

This was already added with the commit bc705ea1cf12 but with
commit 4c4e3b37750f to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agodrivers: net: cpsw: always flush cache of size aligned to PKTALIGN
Lokesh Vutla [Thu, 11 Aug 2016 07:30:59 +0000 (13:00 +0530)]
drivers: net: cpsw: always flush cache of size aligned to PKTALIGN

cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0dffed016]

Fix it by flushing cache of size aligned to PKTALIGN.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoconfigs: dra7xx_evm: enable eth driver model
Mugunthan V N [Wed, 10 Aug 2016 16:35:03 +0000 (22:05 +0530)]
configs: dra7xx_evm: enable eth driver model

Enable eth driver model for dra7xx_evm as cpsw supports
driver model.

This was already added with the commit 641b936fa5ba but with
commit bd7245849f7c to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoARM: dra7xx_evm: Enable regulator DM support
Vignesh R [Wed, 10 Aug 2016 09:47:21 +0000 (15:17 +0530)]
ARM: dra7xx_evm: Enable regulator DM support

Enable DM based regulator framework and also fixed regulator support as
some IPs like mmc use regulators for there functioning.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: dra7xx-evm: add evm_3v3_sd regulator
Vignesh R [Wed, 10 Aug 2016 09:47:20 +0000 (15:17 +0530)]
ARM: dts: dra7xx-evm: add evm_3v3_sd regulator

Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agocommon: image: Add support for post-processing of images
Andreas Dannenberg [Wed, 27 Jul 2016 17:12:39 +0000 (12:12 -0500)]
common: image: Add support for post-processing of images

This commit allows injecting a board/platform/device-specific post-
processing function into the FIT image data loading process, which can
include modifying the size and altering the starting source address of
an image data artifact. This might be desired to do things like strip
headers or footers attached to the images before they were packaged into
the FIT, or to perform operations such as decryption or authentication.
Introduce new configuration option CONFIG_FIT_IMAGE_POST_PROCESS to
allow controlling this feature. If enabled, a platform-specific post-
process function must be provided.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodrivers/sysreset: group sysreset drivers
Max Filippov [Sun, 7 Aug 2016 05:53:00 +0000 (08:53 +0300)]
drivers/sysreset: group sysreset drivers

Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agoARM: non-sec: flush code cacheline aligned
Stefan Agner [Wed, 3 Aug 2016 20:08:55 +0000 (13:08 -0700)]
ARM: non-sec: flush code cacheline aligned

Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
4 years agoi2c: Drop redundant platform data setting in drivers
Simon Glass [Sat, 6 Aug 2016 03:35:27 +0000 (21:35 -0600)]
i2c: Drop redundant platform data setting in drivers

The i2c uclass has a default setting for per_child_platdata_auto_alloc_size
so drivers do not need to set it. Remove this from drivers to avoid
confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-uniphier
Tom Rini [Thu, 11 Aug 2016 14:45:53 +0000 (10:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier

4 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 11 Aug 2016 11:22:55 +0000 (07:22 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

4 years agoARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs
Masahiro Yamada [Wed, 10 Aug 2016 07:08:49 +0000 (16:08 +0900)]
ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs

Currently, only the CPU_ON function is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: add uniphier_cache_set_active_ways()
Masahiro Yamada [Wed, 10 Aug 2016 07:08:48 +0000 (16:08 +0900)]
ARM: uniphier: add uniphier_cache_set_active_ways()

This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: add uniphier_cache_inv_way() to support way invalidation
Masahiro Yamada [Wed, 10 Aug 2016 07:08:47 +0000 (16:08 +0900)]
ARM: uniphier: add uniphier_cache_inv_way() to support way invalidation

This invalidates entries in specified ways of the outer cache.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
Masahiro Yamada [Wed, 10 Aug 2016 07:08:46 +0000 (16:08 +0900)]
ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on

The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line
length and its tags are also managed per 128 byte line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
Masahiro Yamada [Wed, 10 Aug 2016 07:08:45 +0000 (16:08 +0900)]
ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig

Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: move outer cache register macros to .c file
Masahiro Yamada [Wed, 10 Aug 2016 07:08:44 +0000 (16:08 +0900)]
ARM: uniphier: move outer cache register macros to .c file

Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
Masahiro Yamada [Wed, 10 Aug 2016 07:08:43 +0000 (16:08 +0900)]
ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init

The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: export uniphier_cache_enable/disable functions
Masahiro Yamada [Wed, 10 Aug 2016 07:08:42 +0000 (16:08 +0900)]
ARM: uniphier: export uniphier_cache_enable/disable functions

The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM.  The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: move lowlevel debug init code after page table switch
Masahiro Yamada [Wed, 10 Aug 2016 07:08:41 +0000 (16:08 +0900)]
ARM: uniphier: move lowlevel debug init code after page table switch

As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it.  It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: fix ROM boot mode for PH1-sLD3
Masahiro Yamada [Wed, 10 Aug 2016 07:08:40 +0000 (16:08 +0900)]
ARM: uniphier: fix ROM boot mode for PH1-sLD3

Commit 4b50369fb535 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.

The idea here is to check the current page table to determine if
it is a straight map table.  If not, adjust the outer cache register
base.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: refactor L2 zero-touching code in lowlevel_init
Masahiro Yamada [Wed, 10 Aug 2016 07:08:39 +0000 (16:08 +0900)]
ARM: uniphier: refactor L2 zero-touching code in lowlevel_init

Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
Masahiro Yamada [Wed, 10 Aug 2016 07:08:38 +0000 (16:08 +0900)]
ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled

If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable().  The weak
stub avoids the compile error anyway.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: support prefetch and touch operations for outer cache
Masahiro Yamada [Wed, 10 Aug 2016 07:08:37 +0000 (16:08 +0900)]
ARM: uniphier: support prefetch and touch operations for outer cache

The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.

These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: refactor outer cache code
Masahiro Yamada [Wed, 10 Aug 2016 07:08:36 +0000 (16:08 +0900)]
ARM: uniphier: refactor outer cache code

Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.

This reduces the code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoMerge git://www.denx.de/git/u-boot-ppc4xx
Tom Rini [Tue, 9 Aug 2016 11:16:01 +0000 (07:16 -0400)]
Merge git://www.denx.de/git/u-boot-ppc4xx

4 years agoeth: asix88179: Add support for the driver model
Alban Bedel [Tue, 9 Aug 2016 09:10:03 +0000 (11:10 +0200)]
eth: asix88179: Add support for the driver model

Adjust this driver to support driver model for Ethernet.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
4 years agoeth: asix88179: Prepare supporting the driver model
Alban Bedel [Tue, 9 Aug 2016 09:10:02 +0000 (11:10 +0200)]
eth: asix88179: Prepare supporting the driver model

Change the prototype of a few functions to allow resuing the code for
the driver model.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
4 years agoppc4xx: Fix platform support
Dirk Eibach [Mon, 1 Aug 2016 14:34:49 +0000 (16:34 +0200)]
ppc4xx: Fix platform support

Commit "ecc3066 Fix board init code to respect the C runtime environment"
broke platform support for ppc4xx.
start.S prepares a stackframe that is later rendered unusable by appending
the reserved space for global data.
Instead the reserved space has to be put first. Then the stackframe can
be pushed.

I can only test the 405EP OCM case. At least all other ppc4xx boards still
build.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoi2c: i2c-uclass-compat: avoid any BSS usage
Vignesh R [Mon, 25 Jul 2016 10:56:45 +0000 (16:26 +0530)]
i2c: i2c-uclass-compat: avoid any BSS usage

As I2C can be used before DRAM initialization for reading EEPROM,
avoid using static variables stored in BSS, since BSS is in DRAM, which
may not have been initialised yet. Explicitly mark "static global"
variables as belonging to the .data section.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoefi_loader: disk: Sanitize exposed devices
Alexander Graf [Fri, 5 Aug 2016 12:51:47 +0000 (14:51 +0200)]
efi_loader: disk: Sanitize exposed devices

When a target device is 0 bytes long, there's no point in exposing it to
the user. Let's just skip them.

Also, when an offset is passed into the efi disk creation, we should
remove this offset from the total number of sectors we can handle.

This patch fixes both things.

Signed-off-by: Alexander Graf <agraf@suse.de>
4 years agoefi_loader: disk: Fix CONFIG_BLK breakage
Alexander Graf [Fri, 5 Aug 2016 12:49:53 +0000 (14:49 +0200)]
efi_loader: disk: Fix CONFIG_BLK breakage

When using CONFIG_BLK, there were 2 issues:

  1) The name we generate the device with has to match the
     name we set in efi_set_bootdev()

  2) The device we pass into our block functions was wrong,
     we should not rediscover it but just use the already known
     pointer.

This patch fixes both issues.

Signed-off-by: Alexander Graf <agraf@suse.de>
4 years agotiny-printf: Adjust to avoid using data section
Simon Glass [Fri, 5 Aug 2016 03:58:14 +0000 (21:58 -0600)]
tiny-printf: Adjust to avoid using data section

We can pass all the variables down to the functions that need them, and
then everything is on the stack. This is safer than using the data section.

At least on firefly-rk3288, the code size is the same and the data size is
12 bytes smaller:

before:
  18865    2636      40   21541    5425 b/firefly-rk3288/spl/u-boot-spl
after:
  18865    2624      40   21529    5419 b/firefly-rk3288/spl/u-boot-spl

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agoconfigs: k2l_evm: add random eth address support
Mugunthan V N [Tue, 2 Aug 2016 06:31:15 +0000 (12:01 +0530)]
configs: k2l_evm: add random eth address support

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoconfigs: k2e_evm: add random eth address support
Mugunthan V N [Tue, 2 Aug 2016 06:31:14 +0000 (12:01 +0530)]
configs: k2e_evm: add random eth address support

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoconfigs: k2hk_evm: add random eth address support
Mugunthan V N [Tue, 2 Aug 2016 06:31:13 +0000 (12:01 +0530)]
configs: k2hk_evm: add random eth address support

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agodrivers: net: keystone_net: add support for multi slave ethernet
Mugunthan V N [Tue, 2 Aug 2016 06:31:12 +0000 (12:01 +0530)]
drivers: net: keystone_net: add support for multi slave ethernet

Keystone net can have multiple ethernet slaves, currently only
slave 1 is supported by the driver. Register multiple slaves as
individual ethernets to network framework.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agodrivers: net: keystone_net: fix line termination with semi-colon
Mugunthan V N [Tue, 2 Aug 2016 06:31:11 +0000 (12:01 +0530)]
drivers: net: keystone_net: fix line termination with semi-colon

Each line should be terminated by semi-colon. It was not caught
earlier as there is a proper statement. Fix it by changing the
comma with semi-colon.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: dra72-evm: Add mode-gpios entry for mac node
Vignesh R [Tue, 2 Aug 2016 04:44:28 +0000 (10:14 +0530)]
ARM: dts: dra72-evm: Add mode-gpios entry for mac node

On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
4 years agonet: cpsw: Add support to drive gpios for ethernet to be functional
Vignesh R [Tue, 2 Aug 2016 04:44:27 +0000 (10:14 +0530)]
net: cpsw: Add support to drive gpios for ethernet to be functional

On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
4 years agoARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodes
Vignesh R [Tue, 2 Aug 2016 04:44:26 +0000 (10:14 +0530)]
ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodes

PCF8575 does not have any registers hence, offset field needs to be
ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len
with 0 in PCF8575 DT nodes.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>