u-boot.git
4 years agocmd: fdt: add fdt overlay application subcommand
Maxime Ripard [Tue, 5 Jul 2016 08:26:45 +0000 (10:26 +0200)]
cmd: fdt: add fdt overlay application subcommand

The device tree overlays are a good way to deal with user-modifyable
boards or boards with some kind of an expansion mechanism where we can
easily plug new board in (like the BBB or the raspberry pi).

However, so far, the usual mechanism to deal with it was to have in Linux
some driver detecting the expansion boards plugged in and then request
these overlays using the firmware interface.

That works in most cases, but in some cases, you might want to have the
overlays applied before the userspace comes in. Either because the new
board requires some kind of an early initialization, or because your root
filesystem is accessed through that expansion board.

The easiest solution in such a case is to simply have the component before
Linux applying that overlay, removing all these drawbacks.

Reviewed-by: Stefan Agner <stefan@agner.ch>
Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agolibfdt: Add overlay application function
Maxime Ripard [Tue, 5 Jul 2016 08:26:44 +0000 (10:26 +0200)]
libfdt: Add overlay application function

The device tree overlays are a good way to deal with user-modifyable
boards or boards with some kind of an expansion mechanism where we can
easily plug new board in (like the BBB, the Raspberry Pi or the CHIP).

Add a new function to merge overlays with a base device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agolibfdt: Add fdt_setprop_inplace_namelen_partial
Maxime Ripard [Tue, 5 Jul 2016 08:26:43 +0000 (10:26 +0200)]
libfdt: Add fdt_setprop_inplace_namelen_partial

Add a function to modify inplace only a portion of a property..

This is especially useful when the property is an array of values, and you
want to update one of them without changing the DT size.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agolibfdt: Add fdt_getprop_namelen_w
Maxime Ripard [Tue, 5 Jul 2016 08:26:42 +0000 (10:26 +0200)]
libfdt: Add fdt_getprop_namelen_w

Add a function to retrieve a writeable property only by the first
characters of its name.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agolibfdt: Add fdt_path_offset_namelen
Maxime Ripard [Tue, 5 Jul 2016 08:26:41 +0000 (10:26 +0200)]
libfdt: Add fdt_path_offset_namelen

Add a namelen variant of fdt_path_offset to retrieve the node offset using
only a fixed number of characters.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agolibfdt: Fix separator spelling
Maxime Ripard [Tue, 5 Jul 2016 08:26:40 +0000 (10:26 +0200)]
libfdt: Fix separator spelling

The function fdt_path_next_seperator had an obvious mispell. Fix it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agolibfdt: Add max phandle retrieval function
Maxime Ripard [Tue, 5 Jul 2016 08:26:39 +0000 (10:26 +0200)]
libfdt: Add max phandle retrieval function

Add a function to retrieve the highest phandle in a given device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agolibfdt: Add iterator over properties
Maxime Ripard [Tue, 5 Jul 2016 08:26:38 +0000 (10:26 +0200)]
libfdt: Add iterator over properties

Implement a macro based on fdt_first_property_offset and
fdt_next_property_offset that provides a convenience to iterate over all
the properties of a given node.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agolibfdt: Add new headers and defines
Maxime Ripard [Tue, 5 Jul 2016 08:26:37 +0000 (10:26 +0200)]
libfdt: Add new headers and defines

The libfdt overlay support introduces a bunch of new includes and
functions.

Make sure we are able to build it by adding the needed glue.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agovsprintf: Include stdarg for va_list
Maxime Ripard [Tue, 5 Jul 2016 08:26:36 +0000 (10:26 +0200)]
vsprintf: Include stdarg for va_list

vsprintf.h doesn't include the stdarg.h file, which means that it relies on
the files that include vsprintf.h to include stdarg.h as well.

Add an explicit include to avoid build errors when simply including that
file.

Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agoscripts: Makefile.lib: Sanitize DTB names
Maxime Ripard [Tue, 5 Jul 2016 08:26:35 +0000 (10:26 +0200)]
scripts: Makefile.lib: Sanitize DTB names

Having dashes as a separator in the DTB name is a quite common practice.

However, the current code to generate objects from DTBs assumes the
separator is an underscore, leading to a compilation error when building a
device tree with dashes.

Replace all the dashes in the DTB name to generate the symbols name, which
should solve this issue.

Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agocmd: fdt: Narrow the check for fdt addr
Maxime Ripard [Tue, 5 Jul 2016 08:26:34 +0000 (10:26 +0200)]
cmd: fdt: Narrow the check for fdt addr

The current code only checks if the fdt subcommand is fdt addr by checking
whether it starts with 'a'.

Since this is a pretty widely used letter, narrow down that check a bit.

Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Tue, 16 Aug 2016 11:58:41 +0000 (07:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

4 years agox86: Add theadorable-x86-dfi-bt700 board support
Stefan Roese [Mon, 15 Aug 2016 11:50:59 +0000 (13:50 +0200)]
x86: Add theadorable-x86-dfi-bt700 board support

This patch adds support for the BayTrail based theadorable-x86-dfi-bt700
board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard.
The main difference to the DFI baseboard is, that it isn't equipped
with a Super IO chip and uses the internal HS SIO UART (memory mapped
PCI based) as the console UART.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add DFI BT700 BayTrail board support
Stefan Roese [Mon, 15 Aug 2016 11:50:49 +0000 (13:50 +0200)]
x86: Add DFI BT700 BayTrail board support

This patch adds support for the DFI BayTrail BT700 QSeven SoM installed
on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton
NCT6102D Super IO chip providing the UART as console.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: conga-qeval20-qa3: Add SMBus support and SMSC2513 config code
Stefan Roese [Tue, 28 Jun 2016 13:45:13 +0000 (15:45 +0200)]
x86: conga-qeval20-qa3: Add SMBus support and SMSC2513 config code

This patch includes the following changes:

- Remove Designware I2C support from dts as its not used
- Configure SMBus PADs in dts
- Enable I2C commands and I2C support
- Configure SMSC2513 USB hub via SMBus upon startup
- Move environment location to match Minnowmax example
- Enhancement of the default environment

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoi2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail)
Stefan Roese [Tue, 9 Aug 2016 05:41:15 +0000 (07:41 +0200)]
i2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail)

This patch adds support for the SMBus block read/write functionality.
Other protocols like the SMBus quick command need to get added
if this is needed.

This patch also removed the SMBus related defines from the Ivybridge
pch.h header. As they are integrated in this driver and should be
used from here. This change is added in this patch to avoid compile
breakage to keep the source git bisectable.

Tested on a congatec BayTrail board to configure the SMSC2513 USB
hub.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocbfs: Fix incorrect CBFS file header size being used
Yaroslav K [Tue, 9 Aug 2016 03:32:15 +0000 (20:32 -0700)]
cbfs: Fix incorrect CBFS file header size being used

This fixes incorrect filenames in cbfsls output.

Signed-off-by: Yaroslav K. <yar444@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[clean up checkpatch errors and warnings]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: bdinfo: Drop meaningless values
Simon Glass [Sat, 6 Aug 2016 03:57:28 +0000 (21:57 -0600)]
x86: bdinfo: Drop meaningless values

These are not useful on x86 so do not print them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agobdinfo: Don't print out empty DRAM banks
Simon Glass [Sat, 6 Aug 2016 03:57:27 +0000 (21:57 -0600)]
bdinfo: Don't print out empty DRAM banks

There is no sense in printing out DRAM banks of size 0 since this means they
are empty. Skip them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: bayleybay: Add PS/2 keyboard and mouse to ASL file
Bin Meng [Tue, 2 Aug 2016 03:53:53 +0000 (20:53 -0700)]
x86: bayleybay: Add PS/2 keyboard and mouse to ASL file

Without PS/2 keyboard and mouse in the ASL file, Windows does not
see them. No problem for Linux as it probes keyboard and mouse via
the legacy 8042 I/O port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agox86: som-db5800-som-6867: fix SERIRQ on reset
George McCollister [Thu, 28 Jul 2016 14:49:37 +0000 (09:49 -0500)]
x86: som-db5800-som-6867: fix SERIRQ on reset

Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.

Pad configuration for SERIRQ is not set to enable the SERIRQ function
after a reset though strangely, it is on initial boot.

Rebooting from Linux, reset command in u-boot and even pushing the reset
button on the development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agomisc: Add simple driver for some Nuvoton NCT6102D devices
Stefan Roese [Tue, 19 Jul 2016 05:45:46 +0000 (07:45 +0200)]
misc: Add simple driver for some Nuvoton NCT6102D devices

This simple driver provides some functions to control some of the
integrated devices. The watchdog is enabled per default. This driver
adds a function to disable the watchdog. Also the internal legacy
UART (io address 0x3f8/0x2f8) is enabled per default.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
4 years agox86: baytrail: Add SIO HS-UART clock setup
Stefan Roese [Tue, 19 Jul 2016 05:41:25 +0000 (07:41 +0200)]
x86: baytrail: Add SIO HS-UART clock setup

To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: cache.h: Add default for CONFIG_SYS_CACHELINE_SIZE
Stefan Roese [Mon, 18 Jul 2016 10:53:31 +0000 (12:53 +0200)]
x86: cache.h: Add default for CONFIG_SYS_CACHELINE_SIZE

Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE
if it's undefined. This is needed for the xhci driver to compile.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Mention running U-Boot in 64-bit mode in the README
Simon Glass [Sun, 17 Jul 2016 07:23:46 +0000 (01:23 -0600)]
x86: Mention running U-Boot in 64-bit mode in the README

This feature is not supported. Document this, and add some details on how it
might be implemented.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add a reference to README.efi
Simon Glass [Sun, 17 Jul 2016 07:23:45 +0000 (01:23 -0600)]
x86: Add a reference to README.efi

UEFI is commonly used on x86. Add a reference to U-Boot's support for this
in the x86 README.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Mention how to boot a 64-bit kernel from U-Boot
Simon Glass [Sun, 17 Jul 2016 07:22:41 +0000 (01:22 -0600)]
x86: Mention how to boot a 64-bit kernel from U-Boot

The README indicates that this is not supported, but this is no-longer true.
Update the text to indicate this and describe the FIT changes required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: doc: Add note about the debug FSP usage on BayTrail
Stefan Roese [Wed, 13 Jul 2016 06:23:40 +0000 (08:23 +0200)]
x86: doc: Add note about the debug FSP usage on BayTrail

The debug FSP image is bigger in size than the normal FSP image. This
patch adds a small description on how to use this FSP debug version
by changing CONFIG_FSP_ADDR.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: conga-qeval20-qa3: Add missing MAINTERNERS entry
Stefan Roese [Mon, 15 Aug 2016 11:51:15 +0000 (13:51 +0200)]
x86: conga-qeval20-qa3: Add missing MAINTERNERS entry

Add entry for the missing internal UART defconfig to the MAINTAINERS
file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agommc: mmc_legacy: fix the compiler error with disabled CONFIG_DM_MMC_OPS
Jaehoon Chung [Fri, 12 Aug 2016 02:39:05 +0000 (11:39 +0900)]
mmc: mmc_legacy: fix the compiler error with disabled CONFIG_DM_MMC_OPS

To prevent the compiler error, split the checking condition whether
cfg->ops is NULL or not.
It's more clearly, because it's not included in mmc_config structure
when CONFIG_DM_MMC_OPS is disabled.

drivers/mmc/mmc_legacy.c: In function ‘mmc_create’:
drivers/mmc/mmc_legacy.c:118:31: error: ‘const struct mmc_config’ has no member named ‘ops’
drivers/mmc/mmc_legacy.c:118:58: error: ‘const struct mmc_config’ has no member named ‘ops’
make[1]: *** [drivers/mmc/mmc_legacy.o] Error 1

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agommc: send CMD0 before CMD1 for some MMC cards
Yangbo Lu [Tue, 2 Aug 2016 07:33:18 +0000 (15:33 +0800)]
mmc: send CMD0 before CMD1 for some MMC cards

When the MMC framework was added in u-boot, the mmc_go_idle was
added before mmc_send_op_cond_iter in function mmc_send_op_cond
annotating that some cards seemed to need this. Actually, we still
need to do this in function mmc_complete_op_cond for those cards.
This has been verified on Micron MTFC4GACAECN eMMC chip.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
4 years agodefconfig: k2g_evm_defconfig: Enable mmc driver model
Sekhar Nori [Wed, 10 Aug 2016 13:54:06 +0000 (19:24 +0530)]
defconfig: k2g_evm_defconfig: Enable mmc driver model

K2G can benefit from driver model support in the
MMC/SD driver it uses: omap_hsmmc

Enable driver model MMC support for K2G.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: k2g-evm: enable mmc/sd suppport
Sekhar Nori [Wed, 10 Aug 2016 13:54:05 +0000 (19:24 +0530)]
ARM: dts: k2g-evm: enable mmc/sd suppport

The K2G EVM from TI has an SD card slot as
well as onboard eMMC for data storage.

Enable support for these.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: K2G: Add support for MMC controller
Sekhar Nori [Wed, 10 Aug 2016 13:54:04 +0000 (19:24 +0530)]
ARM: dts: K2G: Add support for MMC controller

K2G SoC from TI has two MMC/SD controllers.
Add device tree data for these.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agodrivers: mmc: omap_hsmmc: fix build breakage
Sekhar Nori [Wed, 10 Aug 2016 13:54:03 +0000 (19:24 +0530)]
drivers: mmc: omap_hsmmc: fix build breakage

structure member 'cd_inverted' of omap_hsmmc_data
is available only when OMAP_HSMMC_USE_GPIO is
defined.

When CONFIG_DM_MMC is defined, but not
CONFIG_OMAP_GPIO, this will cause build breakage
in omap_hsmmc driver of the sort:

  CC      drivers/mmc/omap_hsmmc.o
../drivers/mmc/omap_hsmmc.c: In function 'omap_hsmmc_ofdata_to_platdata':
../drivers/mmc/omap_hsmmc.c:1763:6: error: 'struct omap_hsmmc_data' has no member named 'cd_inverted'
  priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
      ^

Fix this by accessing cd_inverted only when
OMAP_HSMMC_USE_GPIO is defined.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agocommon: env_nand: Ensure that we have nand_info[0] prior to use
Tom Rini [Mon, 15 Aug 2016 17:02:15 +0000 (13:02 -0400)]
common: env_nand: Ensure that we have nand_info[0] prior to use

Now that nand_info[] is an array of pointers we need to ensure that it's
been populated prior to use.  We may for example have ENV in NAND set in
configurations that run on boards with and without NAND (where default
env is fine enough, such as omap3_beagle and beagleboard (NAND) vs
beagle xM (no NAND)).

Fixes: b616d9b0a708 ("nand: Embed mtd_info in struct nand_chip")
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <oss@buserror.net>
4 years agotools/env: ensure environment starts at erase block boundary
Andreas Fenkart [Thu, 11 Aug 2016 19:39:17 +0000 (21:39 +0200)]
tools/env: ensure environment starts at erase block boundary

56086921 added support for unaligned environments access.
U-boot itself does not support this:
- env_nand.c fails when using an unaligned offset. It produces an
  error in nand_erase_opts{drivers/mtd/nand/nand_util.c}
- in env_sf/env_flash the unused space at the end is preserved, but
  not in the beginning. block alignment is assumed
- env_sata/env_mmc aligns offset/length to the block size of the
  underlying device. data is silently redirected to the beginning of
  a block

There is seems no use case for unaligned environment. If there is
some useful data at the beginning of the the block (e.g. end of u-boot)
that would be very unsafe. If the redundant environments are hosted by
the same erase block then that invalidates the idea of double buffering.
It might be that unaligned access was allowed in the past, and that
people with legacy u-boot are trapped. But at the time of 56086921
it wasn't supported and due to reasons above I guess it was never
introduced.
I prefer to remove that (unused) feature in favor of simplicity

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
4 years agoxtensa: add support for the 'xtfpga' evaluation board
Chris Zankel [Wed, 10 Aug 2016 15:36:48 +0000 (18:36 +0300)]
xtensa: add support for the 'xtfpga' evaluation board

The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.

 - Avnet Xilinx LX60
 - Avnet Xilinx LX110
 - Avnet Xilinx LX200
 - Xilinx ML605
 - Xilinx KC705

These boards share the same components (open-ethernet, ns16550 serial,
lcd display, flash, etc.).

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the de212 processor
Max Filippov [Wed, 10 Aug 2016 15:36:47 +0000 (18:36 +0300)]
xtensa: add core information for the de212 processor

DE212 is a general purpose xtensa processor without full MMU.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the dc233c processor
Max Filippov [Wed, 10 Aug 2016 15:36:46 +0000 (18:36 +0300)]
xtensa: add core information for the dc233c processor

DC233C is an xtensa processor with full MMUv3 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add core information for the dc232b processor
Chris Zankel [Wed, 10 Aug 2016 15:36:45 +0000 (18:36 +0300)]
xtensa: add core information for the dc232b processor

DC232B is an xtensa processor with full MMUv2 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add support for the xtensa processor architecture [2/2]
Chris Zankel [Wed, 10 Aug 2016 15:36:44 +0000 (18:36 +0300)]
xtensa: add support for the xtensa processor architecture [2/2]

The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoxtensa: add support for the xtensa processor architecture [1/2]
Chris Zankel [Wed, 10 Aug 2016 15:36:43 +0000 (18:36 +0300)]
xtensa: add support for the xtensa processor architecture [1/2]

The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.

This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agovexpress: Check TC2 firmware support before defaulting to nonsec booting
Jon Medhurst \(Tixy\) [Thu, 23 Jun 2016 12:37:32 +0000 (13:37 +0100)]
vexpress: Check TC2 firmware support before defaulting to nonsec booting

The firmware on TC2 needs to be configured appropriately before booting
in nonsec mode will work as expected, so test for this and fall back to
sec mode if required.

Signed-off-by: Jon Medhurst <tixy@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-atmel
Tom Rini [Mon, 15 Aug 2016 21:31:23 +0000 (17:31 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel

4 years agommc: atmel_sdhci: Convert to the driver model support
Wenyou Yang [Wed, 10 Aug 2016 02:51:05 +0000 (10:51 +0800)]
mmc: atmel_sdhci: Convert to the driver model support

Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agodm: atmel: Add driver model support for the ehci driver
Wenyou Yang [Fri, 5 Aug 2016 00:57:35 +0000 (08:57 +0800)]
dm: atmel: Add driver model support for the ehci driver

Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agoARM: at91/dt: Add device tree for SAMA5D2 Xplained
Wenyou Yang [Mon, 25 Jul 2016 09:46:17 +0000 (17:46 +0800)]
ARM: at91/dt: Add device tree for SAMA5D2 Xplained

Add device tree for SAMA5D2 Xplained board.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
4 years agoatmel: Bring in at91 pio4 device tree file and bindings
Wenyou Yang [Wed, 20 Jul 2016 09:16:28 +0000 (17:16 +0800)]
atmel: Bring in at91 pio4 device tree file and bindings

Bring in required device tree file and bindings from Linux.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agopinctrl: at91-pio4: Add pinctrl driver
Wenyou Yang [Wed, 20 Jul 2016 09:16:27 +0000 (17:16 +0800)]
pinctrl: at91-pio4: Add pinctrl driver

AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
4 years agogpio: atmel_pio4: Rework to support DM & DT
Wenyou Yang [Wed, 20 Jul 2016 09:16:26 +0000 (17:16 +0800)]
gpio: atmel_pio4: Rework to support DM & DT

Rework the driver to support driver model and device tree, and
support to regard the pio4 pinctrl device as a child of
atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agogpio: atmel_pio4: Move PIO4 definitions to head file
Wenyou Yang [Wed, 20 Jul 2016 09:16:25 +0000 (17:16 +0800)]
gpio: atmel_pio4: Move PIO4 definitions to head file

In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoclk.h: inline clk_get_by_name()
Andreas Bießmann [Mon, 15 Aug 2016 19:04:41 +0000 (21:04 +0200)]
clk.h: inline clk_get_by_name()

Fix compile warning for non OF_CONTROL builds:

---8<---
In file included from /Volumes/devel/u-boot/drivers/gpio/atmel_pio4.c:10:0:
/Volumes/devel/u-boot/include/clk.h:107:12: warning: 'clk_get_by_name' defined but not used [-Wunused-function]
--->8---

Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Mon, 15 Aug 2016 20:38:39 +0000 (16:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net

4 years agonet: mii: Clean up legacy glue that is not used
Joe Hershberger [Mon, 8 Aug 2016 16:28:41 +0000 (11:28 -0500)]
net: mii: Clean up legacy glue that is not used

The cleanup of the legacy mii registration API that's no longer used now
that the drivers have been converted to use the (more) modern API.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Changes not made by spatch
Joe Hershberger [Mon, 8 Aug 2016 16:28:39 +0000 (11:28 -0500)]
net: mii: Changes not made by spatch

If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.

Make those changes manually.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
For the 4xx related files:
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Fix changes made by spatch
Joe Hershberger [Mon, 8 Aug 2016 16:28:40 +0000 (11:28 -0500)]
net: mii: Fix changes made by spatch

Some of the changes were a bit too complex.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agonet: mii: Use spatch to update miiphy_register
Joe Hershberger [Mon, 8 Aug 2016 16:28:38 +0000 (11:28 -0500)]
net: mii: Use spatch to update miiphy_register

Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoscripts: Add a cocci patch for miiphy_register
Joe Hershberger [Mon, 8 Aug 2016 16:28:37 +0000 (11:28 -0500)]
scripts: Add a cocci patch for miiphy_register

Many Ethernet drivers still use the legacy miiphy API to register their
mdio interface for access to the mdio commands.

This semantic patch will convert the drivers from the legacy adapter API
to the more modern alloc/register API.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agoclk: at91: Add clock driver
Wenyou Yang [Wed, 20 Jul 2016 09:55:12 +0000 (17:55 +0800)]
clk: at91: Add clock driver

The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotpm: atmel_twi: Make compatible with DM I2C busses
mario.six@gdsys.cc [Mon, 18 Jul 2016 11:47:45 +0000 (13:47 +0200)]
tpm: atmel_twi: Make compatible with DM I2C busses

Commit 302c5db ("dm: tpm: Add Driver Model support for tpm_atmel_twi
driver") converted the Atmel TWI TPM driver itself to driver model, but
kept the legacy-style i2c_write/i2c_read calls.

Commit 3e7d940 ("dm: tpm: Every TPM drivers should depends on DM_TPM")
then made DM_I2C a dependency of the driver, effectively forcing users
to turn on CONFIG_DM_I2C_COMPAT to get it to work.

This patch adds the necessary dm_i2c_write/dm_i2c_read calls to make the
driver compatible with DM, but also keeps the legacy calls in ifdefs, so
that the driver is now compatible with both DM and non-DM setups.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
4 years agoi2c: atmel: DT binding for i2c driver
Songjun Wu [Mon, 20 Jun 2016 05:22:39 +0000 (13:22 +0800)]
i2c: atmel: DT binding for i2c driver

DT binding documentation for atmel i2c driver.

Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: atmel: add i2c driver
Songjun Wu [Mon, 20 Jun 2016 05:22:38 +0000 (13:22 +0800)]
i2c: atmel: add i2c driver

Add i2c driver.

Signed-off-by: Songjun Wu <songjun.wu@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
4 years agonet/ethoc: implement MDIO bus and support phylib
Max Filippov [Fri, 5 Aug 2016 15:26:21 +0000 (18:26 +0300)]
net/ethoc: implement MDIO bus and support phylib

Implement MDIO bus read/write functions, initialize the bus and scan for
the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: support private memory configurations
Max Filippov [Fri, 5 Aug 2016 15:26:20 +0000 (18:26 +0300)]
net/ethoc: support private memory configurations

The ethoc device can be configured to have a private memory region
instead of having access to the main memory. In that case egress packets
must be copied into that memory for transmission and pointers to that
memory need to be passed to net_process_received_packet or returned from
the recv callback.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: don't mix virtual and physical addresses
Max Filippov [Fri, 5 Aug 2016 15:26:19 +0000 (18:26 +0300)]
net/ethoc: don't mix virtual and physical addresses

Addresses used in buffer descriptors and passed in platform data or
device tree are physical. Addresses used by CPU to access packet data
and registers are virtual. Don't mix these addresses and use virt_to_phys
for translation.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: support device tree
Max Filippov [Fri, 5 Aug 2016 15:26:18 +0000 (18:26 +0300)]
net/ethoc: support device tree

Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
device configuration from the device tree.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: add CONFIG_DM_ETH support
Max Filippov [Fri, 5 Aug 2016 15:26:17 +0000 (18:26 +0300)]
net/ethoc: add CONFIG_DM_ETH support

Extract reusable parts from ethoc_init, ethoc_set_mac_address,
ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
Add U_BOOT_DRIVER, eth_ops structure and implement required methods.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: use priv instead of dev internally
Max Filippov [Fri, 5 Aug 2016 15:26:16 +0000 (18:26 +0300)]
net/ethoc: use priv instead of dev internally

Don't use physical base address of registers directly, ioremap it first.
Save pointer in private struct ethoc and use that struct in all internal
functions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet/ethoc: add Kconfig entry for the driver
Max Filippov [Fri, 5 Aug 2016 15:26:15 +0000 (18:26 +0300)]
net/ethoc: add Kconfig entry for the driver

Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
only board configuration that uses it and put it into that board's
defconfig.

Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: e1000: Fix the build with driver model and SPI EEPROM
Alban Bedel [Wed, 3 Aug 2016 09:31:03 +0000 (11:31 +0200)]
net: e1000: Fix the build with driver model and SPI EEPROM

When adding support for the driver model the SPI EEPROM feature had
been ignored. Fix the build with both CONFIG_DM_ETH and
CONFIG_E1000_SPI enabled.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: smsc95xx: Use correct get_unaligned functions
Chris Packham [Tue, 12 Jul 2016 21:52:36 +0000 (09:52 +1200)]
net: smsc95xx: Use correct get_unaligned functions

The __get_unaligned_le* functions may not be declared on all platforms.
Instead, get_unaligned_le* should be used. On many platforms both of
these are the same function.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: macb: Fix build error for CONFIG_DM_ETH enabled
Wenyou Yang [Tue, 17 May 2016 05:11:35 +0000 (13:11 +0800)]
net: macb: Fix build error for CONFIG_DM_ETH enabled

Use the right phy_connect() prototype for CONFIGF_DM_ETH.
Support to get the phy interface from dt and set GMAC_UR.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
4 years agoARM: tegra: set vdd_core for Jetson TK1
Bibek Basu [Thu, 11 Aug 2016 22:28:28 +0000 (16:28 -0600)]
ARM: tegra: set vdd_core for Jetson TK1

Program vdd_core for Jetson TK1 to 1V, which is the max safe voltage for
ultra low temperature operations. vdd_cpu and vdd_gpu are already at 1V.

Signed-off-by: Bibek Basu <bbasu@nvidia.com>
(swarren: fixed comments to better match the code)
(swarren: moved board ifdef around data in header, made code generic)
(swarren: fixed typos in commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: reduce CSITE clock from 204M to 136M
Bryan Wu [Thu, 11 Aug 2016 22:28:27 +0000 (16:28 -0600)]
ARM: tegra: reduce CSITE clock from 204M to 136M

The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust the
rate to 136MHz to avoid the warning and stay in spec.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, re-wrote commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: fix trimslice environment location
Stephen Warren [Mon, 8 Aug 2016 19:56:35 +0000 (13:56 -0600)]
ARM: tegra: fix trimslice environment location

Trimslice currently stores its environment at 512KiB into the SPI flash
chip. The U-Boot binary has grown such that the size of the boot image
(which includes the Tegra BCT, padding, and the U-Boot binary) is slightly
larger than 512K now. Consequently, writing the boot image to flash
corrupts the saved environment, and equally, writing to or erasing the
environment will corrupt the bootloader, which in turn will cause the
Tegra boot ROM to enter recovery mode during boot, making it look as if
the system is non-operational. Note that tegra-uboot-flasher writes to
the environment during the flashing process.

Solve this by moving the environment as high as possible in flash. This
will allow the U-Boot binary to roughly double in size before this problem
is hit again, at which point there's nothing we can do anyway since the
binary won't fit into flash.

99% of other Tegra boards store the environment in eMMC and use a negative
value for CONFIG_ENV_OFFSET, which already automatically places the
environment as near the end of boot flash as possible. The 1 remaining
board hard-codes CONFIG_ENV_OFFSET to 2MiB, which allows for plenty more
bloat.

Reported-by: Stephen L Arnold <nerdboy@gentoo.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: move ft_system_setup()
Stephen Warren [Mon, 8 Aug 2016 16:38:34 +0000 (10:38 -0600)]
ARM: tegra: move ft_system_setup()

Currently, ft_system_setup() is implemented by board*.c, which are a bit
of a dumping ground for a bunch of unrelated functionality, and separate
versions exist for pre-Tegra186 and Tegra186. Move the implementation into
a separate file to separate functionality, and allow sharing.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable PCIe controller on p2771-0000
Stephen Warren [Fri, 29 Jul 2016 19:15:06 +0000 (13:15 -0600)]
ARM: tegra: enable PCIe controller on p2771-0000

p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI
connector (which may run at x2 electrically, depending on the board
version and configuration) and a x1 connection to the M.2 slot (which may
not be active, depending on the board version and configuration). This
change enables those.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable SD card on p2771-0000
Stephen Warren [Fri, 29 Jul 2016 19:15:05 +0000 (13:15 -0600)]
ARM: tegra: enable SD card on p2771-0000

Now that clock and reset drivers exist for Tegra186, we can enable the SD
card controller. Now that a BPMP I2C driver exists for Tegra186, we can
communicate with the PMIC to enable power to the SD card. Hook up the DT
content and board code required to make the SD card work.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoARM: tegra: enable I2C buses for P2771-0000
Bryan Wu [Wed, 27 Jul 2016 21:48:22 +0000 (15:48 -0600)]
ARM: tegra: enable I2C buses for P2771-0000

Enable I2C devices in DT and enable building tegra_i2c.c driver.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, commit msg rework, fixed DT node sort order)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoi2c: tegra: add standardized clk/reset API support
Bryan Wu [Fri, 5 Aug 2016 22:10:35 +0000 (16:10 -0600)]
i2c: tegra: add standardized clk/reset API support

clk/reset API was tested on T186 platform and previous chip like
T210/T124 will still use the old APIs.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, simplified some ifdefs, removed indent level inside an ifdef)
(swarren, added comment about the ifdefs)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agopci: tegra: port to standard clock/reset/pwr domain APIs
Stephen Warren [Fri, 5 Aug 2016 22:10:34 +0000 (16:10 -0600)]
pci: tegra: port to standard clock/reset/pwr domain APIs

Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agommc: tegra: port to standard clock/reset APIs
Stephen Warren [Fri, 5 Aug 2016 22:10:33 +0000 (16:10 -0600)]
mmc: tegra: port to standard clock/reset APIs

Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoi2c: add Tegra186 BPMP driver
Stephen Warren [Mon, 8 Aug 2016 17:28:27 +0000 (11:28 -0600)]
i2c: add Tegra186 BPMP driver

On Tegra186, some I2C controllers are directly controlled by the main CPU,
whereas others are controlled by the BPMP, and can only be accessed by the
main CPU via IPC requests to the BPMP. This driver covers the latter case.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agopower domain: add Tegra186 driver
Stephen Warren [Mon, 8 Aug 2016 17:28:26 +0000 (11:28 -0600)]
power domain: add Tegra186 driver

In Tegra186, SoC power domains are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoreset: add Tegra186 reset driver
Stephen Warren [Mon, 8 Aug 2016 17:28:25 +0000 (11:28 -0600)]
reset: add Tegra186 reset driver

In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoclock: add Tegra186 clock driver
Stephen Warren [Mon, 8 Aug 2016 17:28:24 +0000 (11:28 -0600)]
clock: add Tegra186 clock driver

In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agomisc: add Tegra BPMP driver
Stephen Warren [Mon, 8 Aug 2016 15:41:34 +0000 (09:41 -0600)]
misc: add Tegra BPMP driver

The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
4 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 12 Aug 2016 20:00:50 +0000 (16:00 -0400)]
Merge git://git.denx.de/u-boot-dm

4 years agomisc: add "call" uclass op
Stephen Warren [Mon, 8 Aug 2016 15:41:33 +0000 (09:41 -0600)]
misc: add "call" uclass op

The call op requests that the callee pass a message to the underlying HW
or device, wait for a response, and then pass back the response error code
and message to the callee. It is useful for drivers that represent some
kind of messaging or IPC channel to a remote device.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agopower: pmic: act8846: add missing newline to debug statements
John Keeping [Sun, 7 Aug 2016 11:55:40 +0000 (12:55 +0100)]
power: pmic: act8846: add missing newline to debug statements

Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agopower: regulator: act8846: fix reading values
John Keeping [Sun, 7 Aug 2016 11:55:39 +0000 (12:55 +0100)]
power: regulator: act8846: fix reading values

The voltage and control registers need to be looked up from the value in
driver_data.  Adjust the get_value and get_enable functions to match the
corresponding set_* functions.

Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
4 years agofdt: allow fdtdec_get_addr_size_*() to translate addresses
Stephen Warren [Fri, 5 Aug 2016 15:47:51 +0000 (09:47 -0600)]
fdt: allow fdtdec_get_addr_size_*() to translate addresses

Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agofdt_support: fdt_translate_address() blob const correctness
Stephen Warren [Fri, 5 Aug 2016 15:47:50 +0000 (09:47 -0600)]
fdt_support: fdt_translate_address() blob const correctness

The next patch will call fdt_translate_address() from somewhere with a
"const void *blob" rather than a "void *blob", so fdt_translate_address()
must accept a const pointer too. Constify the minimum number of function
parameters to achieve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agokconfig: use bool instead of boolean for type definition attributes
Masahiro Yamada [Fri, 12 Aug 2016 01:26:50 +0000 (10:26 +0900)]
kconfig: use bool instead of boolean for type definition attributes

Linux stopped the use of keyword 'boolean' in Kconfig.

Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agodefconfig: am43xx_evm: enable eth driver model
Mugunthan V N [Thu, 11 Aug 2016 08:57:04 +0000 (14:27 +0530)]
defconfig: am43xx_evm: enable eth driver model

Enable eth driver model for am43xx_evm as cpsw supports
driver model.

This was already added with the commit bc705ea1cf12 but with
commit 4c4e3b37750f to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agodrivers: net: cpsw: always flush cache of size aligned to PKTALIGN
Lokesh Vutla [Thu, 11 Aug 2016 07:30:59 +0000 (13:00 +0530)]
drivers: net: cpsw: always flush cache of size aligned to PKTALIGN

cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0dffed016]

Fix it by flushing cache of size aligned to PKTALIGN.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoconfigs: dra7xx_evm: enable eth driver model
Mugunthan V N [Wed, 10 Aug 2016 16:35:03 +0000 (22:05 +0530)]
configs: dra7xx_evm: enable eth driver model

Enable eth driver model for dra7xx_evm as cpsw supports
driver model.

This was already added with the commit 641b936fa5ba but with
commit bd7245849f7c to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoARM: dra7xx_evm: Enable regulator DM support
Vignesh R [Wed, 10 Aug 2016 09:47:21 +0000 (15:17 +0530)]
ARM: dra7xx_evm: Enable regulator DM support

Enable DM based regulator framework and also fixed regulator support as
some IPs like mmc use regulators for there functioning.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>