board/omap4430panda/omap4430panda.c

   1 /*
   2  * (C) Copyright 2004-2009
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <asm/arch/cpu.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/bits.h>
  27 #include <asm/arch/mux.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/sys_info.h>
  30 #include <asm/arch/clocks.h>
  31 #include <asm/arch/mem.h>
  32 #include <i2c.h>
  33 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
  34 #include <linux/mtd/nand_legacy.h>
  35 #endif
  36
  37 /* EMIF and DMM registers */
  38 #define EMIF1_BASE                      0x4c000000
  39 #define EMIF2_BASE                      0x4d000000
  40 #define DMM_BASE                        0x4e000000
  41 /* EMIF */
  42 #define EMIF_MOD_ID_REV                 0x0000
  43 #define EMIF_STATUS                     0x0004
  44 #define EMIF_SDRAM_CONFIG               0x0008
  45 #define EMIF_LPDDR2_NVM_CONFIG          0x000C
  46 #define EMIF_SDRAM_REF_CTRL             0x0010
  47 #define EMIF_SDRAM_REF_CTRL_SHDW        0x0014
  48 #define EMIF_SDRAM_TIM_1                0x0018
  49 #define EMIF_SDRAM_TIM_1_SHDW           0x001C
  50 #define EMIF_SDRAM_TIM_2                0x0020
  51 #define EMIF_SDRAM_TIM_2_SHDW           0x0024
  52 #define EMIF_SDRAM_TIM_3                0x0028
  53 #define EMIF_SDRAM_TIM_3_SHDW           0x002C
  54 #define EMIF_LPDDR2_NVM_TIM             0x0030
  55 #define EMIF_LPDDR2_NVM_TIM_SHDW        0x0034
  56 #define EMIF_PWR_MGMT_CTRL              0x0038
  57 #define EMIF_PWR_MGMT_CTRL_SHDW         0x003C
  58 #define EMIF_LPDDR2_MODE_REG_DATA       0x0040
  59 #define EMIF_LPDDR2_MODE_REG_CFG        0x0050
  60 #define EMIF_L3_CONFIG                  0x0054
  61 #define EMIF_L3_CFG_VAL_1               0x0058
  62 #define EMIF_L3_CFG_VAL_2               0x005C
  63 #define IODFT_TLGC                      0x0060
  64 #define EMIF_PERF_CNT_1                 0x0080
  65 #define EMIF_PERF_CNT_2                 0x0084
  66 #define EMIF_PERF_CNT_CFG               0x0088
  67 #define EMIF_PERF_CNT_SEL               0x008C
  68 #define EMIF_PERF_CNT_TIM               0x0090
  69 #define EMIF_READ_IDLE_CTRL             0x0098
  70 #define EMIF_READ_IDLE_CTRL_SHDW        0x009c
  71 #define EMIF_ZQ_CONFIG                  0x00C8
  72 #define EMIF_DDR_PHY_CTRL_1             0x00E4
  73 #define EMIF_DDR_PHY_CTRL_1_SHDW        0x00E8
  74 #define EMIF_DDR_PHY_CTRL_2             0x00EC
  75
  76 #define DMM_LISA_MAP_0                  0x0040
  77 #define DMM_LISA_MAP_1                  0x0044
  78 #define DMM_LISA_MAP_2                  0x0048
  79 #define DMM_LISA_MAP_3                  0x004C
  80
  81 #define MR0_ADDR                        0
  82 #define MR1_ADDR                        1
  83 #define MR2_ADDR                        2
  84 #define MR4_ADDR                        4
  85 #define MR10_ADDR                       10
  86 #define MR16_ADDR                       16
  87 #define REF_EN                          0x40000000
  88 /* defines for MR1 */
  89 #define MR1_BL4                         2
  90 #define MR1_BL8                         3
  91 #define MR1_BL16                        4
  92
  93 #define MR1_BT_SEQ                      0
  94 #define BT_INT                          1
  95
  96 #define MR1_WC                          0
  97 #define MR1_NWC                         1
  98
  99 #define MR1_NWR3                        1
 100 #define MR1_NWR4                        2
 101 #define MR1_NWR5                        3
 102 #define MR1_NWR6                        4
 103 #define MR1_NWR7                        5
 104 #define MR1_NWR8                        6
 105
 106 #define MR1_VALUE       ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3)  \
 107                                                         | (MR1_BL8 << 0))
 108
 109 /* defines for MR2 */
 110 #define MR2_RL3_WL1                     1
 111 #define MR2_RL4_WL2                     2
 112 #define MR2_RL5_WL2                     3
 113 #define MR2_RL6_WL3                     4
 114
 115 /* defines for MR10 */
 116 #define MR10_ZQINIT                     0xFF
 117 #define MR10_ZQRESET                    0xC3
 118 #define MR10_ZQCL                       0xAB
 119 #define MR10_ZQCS                       0x56
 120
 121
 122 /* TODO: FREQ update method is not working so shadow registers programming
 123  * is just for same of completeness. This would be safer if auto
 124  * trasnitions are working
 125  */
 126 #define FREQ_UPDATE_EMIF
 127 /* EMIF Needs to be configured@19.2 MHz and shadow registers
 128  * should be programmed for new OPP.
 129  */
 130 /* Elpida 2x2Gbit */
 131 #define SDRAM_CONFIG_INIT               0x80800EB1
 132 #define DDR_PHY_CTRL_1_INIT             0x849FFFF5
 133 #define READ_IDLE_CTRL                  0x000501FF
 134 #define PWR_MGMT_CTRL                   0x4000000f
 135 #define PWR_MGMT_CTRL_OPP100            0x4000000f
 136 #define ZQ_CONFIG                       0x500b3215
 137
 138 #define CS1_MR(mr)      ((mr) | 0x80000000)
 139 struct ddr_regs{
 140         u32 tim1;
 141         u32 tim2;
 142         u32 tim3;
 143         u32 phy_ctrl_1;
 144         u32 ref_ctrl;
 145         u32 config_init;
 146         u32 config_final;
 147         u32 zq_config;
 148         u8 mr1;
 149         u8 mr2;
 150 };
 151 const struct ddr_regs ddr_regs_380_mhz = {
 152         .tim1           = 0x10cb061a,
 153         .tim2           = 0x20350d52,
 154         .tim3           = 0x00b1431f,
 155         .phy_ctrl_1     = 0x849FF408,
 156         .ref_ctrl       = 0x000005ca,
 157         .config_init    = 0x80000eb1,
 158         .config_final   = 0x80001ab1,
 159         .zq_config      = 0x500b3215,
 160         .mr1            = 0x83,
 161         .mr2            = 0x4
 162 };
 163
 164 /*
 165  * Unused timings - but we may need them later
 166  * Keep them commented
 167  */
 168 #if 0
 169 const struct ddr_regs ddr_regs_400_mhz = {
 170         .tim1           = 0x10eb065a,
 171         .tim2           = 0x20370dd2,
 172         .tim3           = 0x00b1c33f,
 173         .phy_ctrl_1     = 0x849FF408,
 174         .ref_ctrl       = 0x00000618,
 175         .config_init    = 0x80000eb1,
 176         .config_final   = 0x80001ab1,
 177         .zq_config      = 0x500b3215,
 178         .mr1            = 0x83,
 179         .mr2            = 0x4
 180 };
 181
 182 const struct ddr_regs ddr_regs_200_mhz = {
 183         .tim1           = 0x08648309,
 184         .tim2           = 0x101b06ca,
 185         .tim3           = 0x0048a19f,
 186         .phy_ctrl_1     = 0x849FF405,
 187         .ref_ctrl       = 0x0000030c,
 188         .config_init    = 0x80000eb1,
 189         .config_final   = 0x80000eb1,
 190         .zq_config      = 0x500b3215,
 191         .mr1            = 0x23,
 192         .mr2            = 0x1
 193 };
 194 #endif
 195
 196 const struct ddr_regs ddr_regs_200_mhz_2cs = {
 197         .tim1           = 0x08648309,
 198         .tim2           = 0x101b06ca,
 199         .tim3           = 0x0048a19f,
 200         .phy_ctrl_1     = 0x849FF405,
 201         .ref_ctrl       = 0x0000030c,
 202         .config_init    = 0x80000eb9,
 203         .config_final   = 0x80000eb9,
 204         .zq_config      = 0xD00b3215,
 205         .mr1            = 0x23,
 206         .mr2            = 0x1
 207 };
 208
 209 const struct ddr_regs ddr_regs_400_mhz_2cs = {
 210         /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
 211         .tim1           = 0x10eb0662,
 212         .tim2           = 0x20370dd2,
 213         .tim3           = 0x00b1c33f,
 214         .phy_ctrl_1     = 0x849FF408,
 215         .ref_ctrl       = 0x00000618,
 216         .config_init    = 0x80000eb9,
 217         .config_final   = 0x80001ab9,
 218         .zq_config      = 0xD00b3215,
 219         .mr1            = 0x83,
 220         .mr2            = 0x4
 221 };
 222
 223 /*******************************************************
 224  * Routine: delay
 225  * Description: spinning delay to use before udelay works
 226  ******************************************************/
 227 static inline void delay(unsigned long loops)
 228 {
 229         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
 230                           "bne 1b" : "=r" (loops) : "0"(loops));
 231 }
 232
 233
 234 void big_delay(unsigned int count)
 235 {
 236         int i;
 237         for (i = 0; i < count; i++)
 238                 delay(1);
 239 }
 240
 241 void reset_phy(unsigned int base)
 242 {
 243         __raw_writel(__raw_readl(base + IODFT_TLGC) | (1 << 10),
 244                                                              base + IODFT_TLGC);
 245 }
 246
 247 /* TODO: FREQ update method is not working so shadow registers programming
 248  * is just for same of completeness. This would be safer if auto
 249  * trasnitions are working
 250  */
 251 static int emif_config(unsigned int base)
 252 {
 253         unsigned int reg_value, rev;
 254         const struct ddr_regs *ddr_regs = NULL;
 255         rev = omap_revision();
 256
 257         if (rev == OMAP4430_ES1_0)
 258                 ddr_regs = &ddr_regs_380_mhz;
 259         else if (rev == OMAP4430_ES2_0)
 260                 ddr_regs = &ddr_regs_200_mhz_2cs;
 261         else if (rev >= OMAP4430_ES2_1)
 262                 ddr_regs = &ddr_regs_400_mhz_2cs;
 263
 264         /*
 265          * set SDRAM CONFIG register
 266          * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
 267          * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
 268          * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
 269          * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
 270          * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
 271          * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2  - 512- 9 column
 272          * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
 273          */
 274         __raw_writel(__raw_readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
 275                                                  base + EMIF_LPDDR2_NVM_CONFIG);
 276         __raw_writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
 277
 278         /* PHY control values */
 279         __raw_writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
 280         __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 281
 282         /*
 283          * EMIF_READ_IDLE_CTRL
 284          */
 285         __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
 286         __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
 287
 288         /*
 289          * EMIF_SDRAM_TIM_1
 290          */
 291         __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
 292         __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
 293
 294         /*
 295          * EMIF_SDRAM_TIM_2
 296          */
 297         __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
 298         __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
 299
 300         /*
 301          * EMIF_SDRAM_TIM_3
 302          */
 303         __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
 304         __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
 305
 306         __raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
 307
 308         /*
 309          * poll MR0 register (DAI bit)
 310          * REG_CS[31] = 0 -- Mode register command to CS0
 311          * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
 312          * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
 313          */
 314
 315         __raw_writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
 316
 317         do {
 318                 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 319         } while (reg_value & 1);
 320
 321         __raw_writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
 322
 323         do {
 324                 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 325         } while (reg_value & 1);
 326
 327
 328         /* set MR10 register */
 329         __raw_writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
 330         __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
 331         __raw_writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
 332         __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
 333
 334         /* wait for tZQINIT=1us  */
 335         delay(10);
 336
 337         /* set MR1 register */
 338         __raw_writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
 339         __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
 340         __raw_writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
 341         __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
 342
 343         /* set MR2 register RL=6 for OPP100 */
 344         __raw_writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
 345         __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
 346         __raw_writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
 347         __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
 348
 349         /* Set SDRAM CONFIG register again here with final RL-WL value */
 350         __raw_writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
 351         __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
 352
 353         /*
 354          * EMIF_SDRAM_REF_CTRL
 355          * refresh rate = DDR_CLK / reg_refresh_rate
 356          * 3.9 uS = (400MHz)    / reg_refresh_rate
 357          */
 358         __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
 359         __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
 360
 361         /* set MR16 register */
 362         __raw_writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
 363         __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
 364         __raw_writel(CS1_MR(MR16_ADDR | REF_EN),
 365                                                base + EMIF_LPDDR2_MODE_REG_CFG);
 366         __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
 367
 368         /* LPDDR2 init complete */
 369
 370         return 0;
 371 }
 372 /*****************************************
 373  * Routine: ddr_init
 374  * Description: Configure DDR
 375  * EMIF1 -- CS0 -- DDR1 (256 MB)
 376  * EMIF2 -- CS0 -- DDR2 (256 MB)
 377  *****************************************/
 378 static void ddr_init(void)
 379 {
 380         unsigned int base_addr, rev;
 381         rev = omap_revision();
 382
 383         if (rev == OMAP4430_ES1_0) {
 384                 /* Configurte the Control Module DDRIO device */
 385                 __raw_writel(0x1c1c1c1c, 0x4A100638);
 386                 __raw_writel(0x1c1c1c1c, 0x4A10063c);
 387                 __raw_writel(0x1c1c1c1c, 0x4A100640);
 388                 __raw_writel(0x1c1c1c1c, 0x4A100648);
 389                 __raw_writel(0x1c1c1c1c, 0x4A10064c);
 390                 __raw_writel(0x1c1c1c1c, 0x4A100650);
 391                 /* LPDDR2IO set to NMOS PTV */
 392                 __raw_writel(0x00ffc000, 0x4A100704);
 393         } else if (rev == OMAP4430_ES2_0) {
 394                 __raw_writel(0x9e9e9e9e, 0x4A100638);
 395                 __raw_writel(0x9e9e9e9e, 0x4A10063c);
 396                 __raw_writel(0x9e9e9e9e, 0x4A100640);
 397                 __raw_writel(0x9e9e9e9e, 0x4A100648);
 398                 __raw_writel(0x9e9e9e9e, 0x4A10064c);
 399                 __raw_writel(0x9e9e9e9e, 0x4A100650);
 400                 /* LPDDR2IO set to NMOS PTV */
 401                 __raw_writel(0x00ffc000, 0x4A100704);
 402         }
 403
 404         /*
 405          * DMM Configuration
 406          */
 407
 408         /* Both EMIFs 128 byte interleaved*/
 409         if (rev == OMAP4430_ES1_0)
 410                 __raw_writel(0x80540300, DMM_BASE + DMM_LISA_MAP_0);
 411         else
 412                 __raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
 413
 414         __raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
 415         __raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
 416
 417         /* DDR needs to be initialised @ 19.2 MHz
 418          * So put core DPLL in bypass mode
 419          * Configure the Core DPLL but don't lock it
 420          */
 421         configure_core_dpll_no_lock();
 422
 423         __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
 424         __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 425
 426         base_addr = EMIF1_BASE;
 427         emif_config(base_addr);
 428
 429         /* Configure EMIF24D */
 430         base_addr = EMIF2_BASE;
 431         emif_config(base_addr);
 432         /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
 433         lock_core_dpll_shadow();
 434         /* TODO: SDC needs few hacks to get DDR freq update working */
 435
 436         /* Set DLL_OVERRIDE = 0 */
 437         __raw_writel(0, CM_DLL_CTRL);
 438
 439         delay(200);
 440
 441         /* Check for DDR PHY ready for EMIF1 & EMIF2 */
 442         while (!(__raw_readl(EMIF1_BASE + EMIF_STATUS) & 4) ||
 443                                    !(__raw_readl(EMIF2_BASE + EMIF_STATUS) & 4))
 444                 ;
 445
 446         /* Reprogram the DDR PYHY Control register */
 447         /* PHY control values */
 448
 449         sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
 450         sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
 451
 452         /* Put the Core Subsystem PD to ON State */
 453
 454         __raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
 455         __raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 456
 457         /* SYSTEM BUG:
 458          * In n a specific situation, the OCP interface between the DMM and
 459          * EMIF may hang.
 460          * 1. A TILER port is used to perform 2D burst writes of
 461          *       width 1 and height 8
 462          * 2. ELLAn port is used to perform reads
 463          * 3. All accesses are routed to the same EMIF controller
 464          *
 465          * Work around to avoid this issue REG_SYS_THRESH_MAX value should
 466          * be kept higher than default 0x7. As per recommondation 0x0A will
 467          * be used for better performance with REG_LL_THRESH_MAX = 0x00
 468          */
 469         if (rev == OMAP4430_ES1_0) {
 470                 __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
 471                 __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
 472         }
 473
 474         /*
 475          * DMM : DMM_LISA_MAP_0(Section_0)
 476          * [31:24] SYS_ADDR             0x80
 477          * [22:20] SYS_SIZE             0x7 - 2Gb
 478          * [19:18] SDRC_INTLDMM         0x1 - 128 byte
 479          * [17:16] SDRC_ADDRSPC         0x0
 480          * [9:8] SDRC_MAP               0x3
 481          * [7:0] SDRC_ADDR              0X0
 482          */
 483         reset_phy(EMIF1_BASE);
 484         reset_phy(EMIF2_BASE);
 485
 486         __raw_writel(0, 0x80000000);
 487         __raw_writel(0, 0x80000000);
 488 }
 489 /*****************************************
 490  * Routine: board_init
 491  * Description: Early hardware init.
 492  *****************************************/
 493 int board_init(void)
 494 {
 495         return 0;
 496 }
 497
 498 /*************************************************************
 499  * Routine: get_mem_type(void) - returns the kind of memory connected
 500  * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
 501  *************************************************************/
 502 u32 get_mem_type(void)
 503 {
 504         /* no nand, so return GPMC_NONE */
 505         return GPMC_NONE;
 506 }
 507
 508 /*****************************************
 509  * Routine: secure_unlock
 510  * Description: Setup security registers for access
 511  * (GP Device only)
 512  *****************************************/
 513 void secure_unlock_mem(void)
 514 {
 515         /* Permission values for registers -Full fledged permissions to all */
 516         #define UNLOCK_1 0xFFFFFFFF
 517         #define UNLOCK_2 0x00000000
 518         #define UNLOCK_3 0x0000FFFF
 519
 520         /* Protection Module Register Target APE (PM_RT)*/
 521         __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
 522         __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
 523         __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
 524         __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
 525
 526         __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
 527         __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
 528         __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
 529
 530         __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
 531         __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
 532         __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
 533         __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
 534
 535         /* IVA Changes */
 536         __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
 537         __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
 538         __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
 539
 540         __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
 541 }
 542
 543 /**********************************************************
 544  * Routine: try_unlock_sram()
 545  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 546  *  general use.
 547  ***********************************************************/
 548 void try_unlock_memory(void)
 549 {
 550         /* if GP device unlock device SRAM for general use */
 551         /* secure code breaks for Secure/Emulation device - HS/E/T*/
 552 }
 553
 554
 555 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
 556 static int scale_vcores(void)
 557 {
 558         unsigned int rev = omap_revision();
 559         /* For VC bypass only VCOREx_CGF_FORCE  is necessary and
 560          * VCOREx_CFG_VOLTAGE  changes can be discarded
 561          */
 562         /* PRM_VC_CFG_I2C_MODE */
 563         __raw_writel(0, 0x4A307BA8);
 564
 565         /* PRM_VC_CFG_I2C_CLK */
 566         __raw_writel(0x6026, 0x4A307BAC);
 567
 568         /* set VCORE1 force VSEL */
 569         /* PRM_VC_VAL_BYPASS) */
 570         if (rev == OMAP4430_ES1_0)
 571                 __raw_writel(0x3B5512, 0x4A307BA0);
 572         else
 573                 __raw_writel(0x3A5512, 0x4A307BA0);
 574
 575         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
 576         while (__raw_readl(0x4A307BA0) & 0x1000000)
 577                 ;
 578
 579         /* PRM_IRQSTATUS_MPU */
 580         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
 581
 582         /* FIXME: set VCORE2 force VSEL, Check the reset value */
 583         /* PRM_VC_VAL_BYPASS) */
 584         if (rev == OMAP4430_ES1_0)
 585                 __raw_writel(0x315B12, 0x4A307BA0);
 586         else
 587                 __raw_writel(0x295B12, 0x4A307BA0);
 588
 589         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
 590         while (__raw_readl(0x4A307BA0) & 0x1000000)
 591                 ;
 592
 593         /* PRM_IRQSTATUS_MPU */
 594         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
 595
 596         /*/set VCORE3 force VSEL */
 597         /* PRM_VC_VAL_BYPASS */
 598         switch (rev) {
 599         case OMAP4430_ES1_0:
 600                 __raw_writel(0x316112, 0x4A307BA0);
 601                 break;
 602         case OMAP4430_ES2_0:
 603                 __raw_writel(0x296112, 0x4A307BA0);
 604                 break;
 605         case OMAP4430_ES2_1:
 606                 __raw_writel(0x2A6112, 0x4A307BA0);
 607                 break;
 608         }
 609         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
 610         while (__raw_readl(0x4A307BA0) & 0x1000000)
 611                 ;
 612
 613         /* PRM_IRQSTATUS_MPU */
 614         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
 615
 616         return 0;
 617 }
 618 #endif
 619
 620 /**********************************************************
 621  * Routine: s_init
 622  * Description: Does early system init of muxing and clocks.
 623  * - Called path is with SRAM stack.
 624  **********************************************************/
 625
 626 void s_init(void)
 627 {
 628         unsigned int rev = omap_revision();
 629
 630         set_muxconf_regs();
 631         delay(100);
 632
 633         /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
 634         /* Currently SMI in Kernel on ES2 devices seems to have an isse
 635          * Once that is resolved, we can postpone this config to kernel
 636          */
 637         /* setup_auxcr(get_device_type(), external_boot); */
 638
 639         ddr_init();
 640
 641 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
 642 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
 643         scale_vcores();
 644 #endif
 645         prcm_init();
 646
 647         if (rev != OMAP4430_ES1_0) {
 648                 if (__raw_readl(0x4805D138) & (1<<22)) {
 649                         /* enable software ioreq */
 650                         sr32(0x4A30a31C, 8, 1, 0x1);
 651                         /* set for sys_clk (38.4MHz) */
 652                         sr32(0x4A30a31C, 1, 2, 0x0);
 653                         /* set divisor to 2 */
 654                         sr32(0x4A30a31C, 16, 4, 0x1);
 655                         /* set the clock source to active */
 656                         sr32(0x4A30a110, 0, 1, 0x1);
 657                         /* enable clocks */
 658                         sr32(0x4A30a110, 2, 2, 0x3);
 659                 } else {
 660                         /* enable software ioreq */
 661                         sr32(0x4A30a314, 8, 1, 0x1);
 662                         /* set for PER_DPLL */
 663                         sr32(0x4A30a314, 1, 2, 0x2);
 664                         /* set divisor to 16 */
 665                         sr32(0x4A30a314, 16, 4, 0xf);
 666                         /* set the clock source to active */
 667                         sr32(0x4A30a110, 0, 1, 0x1);
 668                         /* enable clocks */
 669                         sr32(0x4A30a110, 2, 2, 0x3);
 670                 }
 671         }
 672
 673 }
 674
 675 /*******************************************************
 676  * Routine: misc_init_r
 677  * Description: Init ethernet (done here so udelay works)
 678  ********************************************************/
 679 int misc_init_r(void)
 680 {
 681         return 0;
 682 }
 683
 684 /******************************************************
 685  * Routine: wait_for_command_complete
 686  * Description: Wait for posting to finish on watchdog
 687  ******************************************************/
 688 void wait_for_command_complete(unsigned int wd_base)
 689 {
 690         int pending = 1;
 691         do {
 692                 pending = __raw_readl(wd_base + WWPS);
 693         } while (pending);
 694 }
 695
 696 /*******************************************************************
 697  * Routine:ether_init
 698  * Description: take the Ethernet controller out of reset and wait
 699  *                 for the EEPROM load to complete.
 700  ******************************************************************/
 701
 702 /**********************************************
 703  * Routine: dram_init
 704  * Description: sets uboots idea of sdram size
 705  **********************************************/
 706 int dram_init(void)
 707 {
 708         return 0;
 709 }
 710
 711 #define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000
 712 #if 1
 713 #define M0_SAFE M0
 714 #define M1_SAFE M1
 715 #define M2_SAFE M2
 716 #define M4_SAFE M4
 717 #define M7_SAFE M7
 718 #define M3_SAFE M3
 719 #define M5_SAFE M5
 720 #define M6_SAFE M6
 721 #else
 722 #define M0_SAFE M7
 723 #define M1_SAFE M7
 724 #define M2_SAFE M7
 725 #define M4_SAFE M7
 726 #define M7_SAFE M7
 727 #define M3_SAFE M7
 728 #define M5_SAFE M7
 729 #define M6_SAFE M7
 730 #endif
 731 #define         MV(OFFSET, VALUE) \
 732                         __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET));
 733 #define         MV1(OFFSET, VALUE) \
 734                       __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET));
 735
 736 #define         CP(x)   (CONTROL_PADCONF_##x)
 737 #define         WK(x)   (CONTROL_WKUP_##x)
 738 /*
 739  * IEN  - Input Enable
 740  * IDIS - Input Disable
 741  * PTD  - Pull type Down
 742  * PTU  - Pull type Up
 743  * DIS  - Pull type selection is inactive
 744  * EN   - Pull type selection is active
 745  * M0   - Mode 0
 746  * The commented string gives the final mux configuration for that pin
 747  */
 748
 749 struct omap4panda_mux {
 750         unsigned int ads;
 751         unsigned int value;
 752 };
 753
 754 static const struct omap4panda_mux omap4panda_mux[] = {
 755         { OMAP44XX_CTRL_BASE + CP(GPMC_AD0),
 756                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
 757         { OMAP44XX_CTRL_BASE + CP(GPMC_AD1),
 758                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat1 */ },
 759         { OMAP44XX_CTRL_BASE + CP(GPMC_AD2),
 760                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat2 */ },
 761         { OMAP44XX_CTRL_BASE + CP(GPMC_AD3),
 762                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat3 */ },
 763         { OMAP44XX_CTRL_BASE + CP(GPMC_AD4),
 764                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat4 */ },
 765         { OMAP44XX_CTRL_BASE + CP(GPMC_AD5),
 766                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat5 */ },
 767         { OMAP44XX_CTRL_BASE + CP(GPMC_AD6),
 768                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat6 */ },
 769         { OMAP44XX_CTRL_BASE + CP(GPMC_AD7),
 770                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat7 */ },
 771         { OMAP44XX_CTRL_BASE + CP(GPMC_AD8),
 772                      PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3  /* gpio_32 */ },
 773         { OMAP44XX_CTRL_BASE + CP(GPMC_AD9),
 774                                                 PTU | IEN | M3  /* gpio_33 */ },
 775         { OMAP44XX_CTRL_BASE + CP(GPMC_AD10),
 776                                                 PTU | IEN | M3  /* gpio_34 */ },
 777         { OMAP44XX_CTRL_BASE + CP(GPMC_AD11),
 778                                                 PTU | IEN | M3  /* gpio_35 */ },
 779         { OMAP44XX_CTRL_BASE + CP(GPMC_AD12),
 780                                                 PTU | IEN | M3  /* gpio_36 */ },
 781         { OMAP44XX_CTRL_BASE + CP(GPMC_AD13),
 782                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_37 */ },
 783         { OMAP44XX_CTRL_BASE + CP(GPMC_AD14),
 784                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_38 */ },
 785         { OMAP44XX_CTRL_BASE + CP(GPMC_AD15),
 786                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_39 */ },
 787         { OMAP44XX_CTRL_BASE + CP(GPMC_A16), M3  /* gpio_40 */ },
 788         { OMAP44XX_CTRL_BASE + CP(GPMC_A17), PTD | M3  /* gpio_41 */ },
 789         { OMAP44XX_CTRL_BASE + CP(GPMC_A18),
 790                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row6 */ },
 791         { OMAP44XX_CTRL_BASE + CP(GPMC_A19),
 792                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row7 */ },
 793         { OMAP44XX_CTRL_BASE + CP(GPMC_A20),
 794                                                       IEN | M3  /* gpio_44 */ },
 795         { OMAP44XX_CTRL_BASE + CP(GPMC_A21), M3  /* gpio_45 */ },
 796         { OMAP44XX_CTRL_BASE + CP(GPMC_A22), M3  /* gpio_46 */ },
 797         { OMAP44XX_CTRL_BASE + CP(GPMC_A23),
 798                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col7 */ },
 799         { OMAP44XX_CTRL_BASE + CP(GPMC_A24), PTD | M3  /* gpio_48 */ },
 800         { OMAP44XX_CTRL_BASE + CP(GPMC_A25), PTD | M3  /* gpio_49 */ },
 801         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS0), M3  /* gpio_50 */ },
 802         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS1), IEN | M3  /* gpio_51 */ },
 803         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS2), IEN | M3  /* gpio_52 */ },
 804         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS3), IEN | M3  /* gpio_53 */ },
 805         { OMAP44XX_CTRL_BASE + CP(GPMC_NWP), M3  /* gpio_54 */ },
 806         { OMAP44XX_CTRL_BASE + CP(GPMC_CLK), PTD | M3  /* gpio_55 */ },
 807         { OMAP44XX_CTRL_BASE + CP(GPMC_NADV_ALE), M3  /* gpio_56 */ },
 808         { OMAP44XX_CTRL_BASE + CP(GPMC_NOE),
 809                       PTU | IEN | OFF_EN | OFF_OUT_PTD | M1  /* sdmmc2_clk */ },
 810         { OMAP44XX_CTRL_BASE + CP(GPMC_NWE),
 811                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_cmd */ },
 812         { OMAP44XX_CTRL_BASE + CP(GPMC_NBE0_CLE), M3  /* gpio_59 */ },
 813         { OMAP44XX_CTRL_BASE + CP(GPMC_NBE1), PTD | M3  /* gpio_60 */ },
 814         { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT0), PTU | IEN | M3  /* gpio_61 */ },
 815         { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT1),
 816                        PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_62 */ },
 817         { OMAP44XX_CTRL_BASE + CP(C2C_DATA11), PTD | M3  /* gpio_100 */ },
 818         { OMAP44XX_CTRL_BASE + CP(C2C_DATA12), PTD | IEN | M3  /* gpio_101 */ },
 819         { OMAP44XX_CTRL_BASE + CP(C2C_DATA13), PTD | M3  /* gpio_102 */ },
 820         { OMAP44XX_CTRL_BASE + CP(C2C_DATA14), M1  /* dsi2_te0 */ },
 821         { OMAP44XX_CTRL_BASE + CP(C2C_DATA15), PTD | M3  /* gpio_104 */ },
 822         { OMAP44XX_CTRL_BASE + CP(HDMI_HPD), M0  /* hdmi_hpd */ },
 823         { OMAP44XX_CTRL_BASE + CP(HDMI_CEC), M0  /* hdmi_cec */ },
 824         { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SCL), PTU | M0  /* hdmi_ddc_scl */ },
 825         { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SDA),
 826                                            PTU | IEN | M0  /* hdmi_ddc_sda */ },
 827         { OMAP44XX_CTRL_BASE + CP(CSI21_DX0), IEN | M0  /* csi21_dx0 */ },
 828         { OMAP44XX_CTRL_BASE + CP(CSI21_DY0), IEN | M0  /* csi21_dy0 */ },
 829         { OMAP44XX_CTRL_BASE + CP(CSI21_DX1), IEN | M0  /* csi21_dx1 */ },
 830         { OMAP44XX_CTRL_BASE + CP(CSI21_DY1), IEN | M0  /* csi21_dy1 */ },
 831         { OMAP44XX_CTRL_BASE + CP(CSI21_DX2), IEN | M0  /* csi21_dx2 */ },
 832         { OMAP44XX_CTRL_BASE + CP(CSI21_DY2), IEN | M0  /* csi21_dy2 */ },
 833         { OMAP44XX_CTRL_BASE + CP(CSI21_DX3), PTD | M7  /* csi21_dx3 */ },
 834         { OMAP44XX_CTRL_BASE + CP(CSI21_DY3), PTD | M7  /* csi21_dy3 */ },
 835         { OMAP44XX_CTRL_BASE + CP(CSI21_DX4),
 836                          PTD | OFF_EN | OFF_PD | OFF_IN | M7  /* csi21_dx4 */ },
 837         { OMAP44XX_CTRL_BASE + CP(CSI21_DY4),
 838                          PTD | OFF_EN | OFF_PD | OFF_IN | M7  /* csi21_dy4 */ },
 839         { OMAP44XX_CTRL_BASE + CP(CSI22_DX0), IEN | M0  /* csi22_dx0 */ },
 840         { OMAP44XX_CTRL_BASE + CP(CSI22_DY0), IEN | M0  /* csi22_dy0 */ },
 841         { OMAP44XX_CTRL_BASE + CP(CSI22_DX1), IEN | M0  /* csi22_dx1 */ },
 842         { OMAP44XX_CTRL_BASE + CP(CSI22_DY1), IEN | M0  /* csi22_dy1 */ },
 843         { OMAP44XX_CTRL_BASE + CP(CAM_SHUTTER),
 844                         OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* cam_shutter */ },
 845         { OMAP44XX_CTRL_BASE + CP(CAM_STROBE),
 846                          OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* cam_strobe */ },
 847         { OMAP44XX_CTRL_BASE + CP(CAM_GLOBALRESET),
 848                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_83 */ },
 849         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_CLK),
 850            PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_clk */ },
 851         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_STP),
 852                            OFF_EN | OFF_OUT_PTD | M4  /* usbb1_ulpiphy_stp */ },
 853         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DIR),
 854                  IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dir */ },
 855         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_NXT),
 856                  IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_nxt */ },
 857         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT0),
 858                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat0 */ },
 859         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT1),
 860                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat1 */ },
 861         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT2),
 862                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat2 */ },
 863         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT3),
 864                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat3 */ },
 865         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT4),
 866                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat4 */ },
 867         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT5),
 868                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat5 */ },
 869         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT6),
 870                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat6 */ },
 871         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT7),
 872                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat7 */ },
 873         { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_DATA),
 874                    IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usbb1_hsic_data */ },
 875         { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_STROBE),
 876                  IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usbb1_hsic_strobe */ },
 877         { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DP),
 878                                                IEN | M0  /* usbc1_icusb_dp */ },
 879         { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DM),
 880                                                IEN | M0  /* usbc1_icusb_dm */ },
 881         { OMAP44XX_CTRL_BASE + CP(SDMMC1_CLK),
 882                             PTU | OFF_EN | OFF_OUT_PTD | M0  /* sdmmc1_clk */ },
 883         { OMAP44XX_CTRL_BASE + CP(SDMMC1_CMD),
 884                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_cmd */ },
 885         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT0),
 886                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat0 */ },
 887         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT1),
 888                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat1 */ },
 889         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT2),
 890                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat2 */ },
 891         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT3),
 892                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat3 */ },
 893         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT4),
 894                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat4 */ },
 895         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT5),
 896                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat5 */ },
 897         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT6),
 898                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat6 */ },
 899         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT7),
 900                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat7 */ },
 901         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_CLKX),
 902                    IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp2_clkx */ },
 903         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DR),
 904                          IEN | OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp2_dr */ },
 905         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DX),
 906                                OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp2_dx */ },
 907         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_FSX),
 908                     IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp2_fsx */ },
 909         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_CLKX),
 910                                            IEN | M1  /* abe_slimbus1_clock */ },
 911         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DR),
 912                                             IEN | M1  /* abe_slimbus1_data */ },
 913         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DX),
 914                                OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp1_dx */ },
 915         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_FSX),
 916                     IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp1_fsx */ },
 917         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_UL_DATA),
 918              PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_ul_data */ },
 919         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_DL_DATA),
 920              PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_dl_data */ },
 921         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_FRAME),
 922                PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_frame */ },
 923         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_LB_CLK),
 924               PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_lb_clk */ },
 925         { OMAP44XX_CTRL_BASE + CP(ABE_CLKS),
 926                     PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_clks */ },
 927         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_CLK1), M0  /* abe_dmic_clk1 */ },
 928         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN1),
 929                                                 IEN | M0  /* abe_dmic_din1 */ },
 930         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN2),
 931                                                 IEN | M0  /* abe_dmic_din2 */ },
 932         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN3),
 933                                                 IEN | M0  /* abe_dmic_din3 */ },
 934         { OMAP44XX_CTRL_BASE + CP(UART2_CTS), PTU | IEN | M0  /* uart2_cts */ },
 935         { OMAP44XX_CTRL_BASE + CP(UART2_RTS), M0  /* uart2_rts */ },
 936         { OMAP44XX_CTRL_BASE + CP(UART2_RX), PTU | IEN | M0  /* uart2_rx */ },
 937         { OMAP44XX_CTRL_BASE + CP(UART2_TX), M0  /* uart2_tx */ },
 938         { OMAP44XX_CTRL_BASE + CP(HDQ_SIO), M3  /* gpio_127 */ },
 939         { OMAP44XX_CTRL_BASE + CP(I2C1_SCL), PTU | IEN | M0  /* i2c1_scl */ },
 940         { OMAP44XX_CTRL_BASE + CP(I2C1_SDA), PTU | IEN | M0  /* i2c1_sda */ },
 941         { OMAP44XX_CTRL_BASE + CP(I2C2_SCL), PTU | IEN | M0  /* i2c2_scl */ },
 942         { OMAP44XX_CTRL_BASE + CP(I2C2_SDA), PTU | IEN | M0  /* i2c2_sda */ },
 943         { OMAP44XX_CTRL_BASE + CP(I2C3_SCL), PTU | IEN | M0  /* i2c3_scl */ },
 944         { OMAP44XX_CTRL_BASE + CP(I2C3_SDA), PTU | IEN | M0  /* i2c3_sda */ },
 945         { OMAP44XX_CTRL_BASE + CP(I2C4_SCL), PTU | IEN | M0  /* i2c4_scl */ },
 946         { OMAP44XX_CTRL_BASE + CP(I2C4_SDA), PTU | IEN | M0  /* i2c4_sda */ },
 947         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CLK),
 948                         IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_clk */ },
 949         { OMAP44XX_CTRL_BASE + CP(MCSPI1_SOMI),
 950                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_somi */ },
 951         { OMAP44XX_CTRL_BASE + CP(MCSPI1_SIMO),
 952                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_simo */ },
 953         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS0),
 954                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_cs0 */ },
 955         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS1),
 956                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3  /* mcspi1_cs1 */ },
 957         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS2),
 958                               PTU | OFF_EN | OFF_OUT_PTU | M3  /* gpio_139 */ },
 959         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS3), PTU | IEN | M3  /* gpio_140 */ },
 960         { OMAP44XX_CTRL_BASE + CP(UART3_CTS_RCTX),
 961                                                PTU | IEN | M0  /* uart3_tx */ },
 962         { OMAP44XX_CTRL_BASE + CP(UART3_RTS_SD), M0  /* uart3_rts_sd */ },
 963         { OMAP44XX_CTRL_BASE + CP(UART3_RX_IRRX), IEN | M0  /* uart3_rx */ },
 964         { OMAP44XX_CTRL_BASE + CP(UART3_TX_IRTX), M0  /* uart3_tx */ },
 965         { OMAP44XX_CTRL_BASE + CP(SDMMC5_CLK),
 966                       PTU | IEN | OFF_EN | OFF_OUT_PTD | M0  /* sdmmc5_clk */ },
 967         { OMAP44XX_CTRL_BASE + CP(SDMMC5_CMD),
 968                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_cmd */ },
 969         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT0),
 970                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat0 */ },
 971         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT1),
 972                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat1 */ },
 973         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT2),
 974                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat2 */ },
 975         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT3),
 976                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat3 */ },
 977         { OMAP44XX_CTRL_BASE + CP(MCSPI4_CLK),
 978                         IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_clk */ },
 979         { OMAP44XX_CTRL_BASE + CP(MCSPI4_SIMO),
 980                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_simo */ },
 981         { OMAP44XX_CTRL_BASE + CP(MCSPI4_SOMI),
 982                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_somi */ },
 983         { OMAP44XX_CTRL_BASE + CP(MCSPI4_CS0),
 984                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_cs0 */ },
 985         { OMAP44XX_CTRL_BASE + CP(UART4_RX), IEN | M0  /* uart4_rx */ },
 986         { OMAP44XX_CTRL_BASE + CP(UART4_TX), M0  /* uart4_tx */ },
 987         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_CLK),
 988                                                      IEN | M3  /* gpio_157 */ },
 989         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_STP),
 990                                                 IEN | M5  /* dispc2_data23 */ },
 991         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DIR),
 992                                                 IEN | M5  /* dispc2_data22 */ },
 993         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_NXT),
 994                                                 IEN | M5  /* dispc2_data21 */ },
 995         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT0),
 996                                                 IEN | M5  /* dispc2_data20 */ },
 997         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT1),
 998                                                 IEN | M5  /* dispc2_data19 */ },
 999         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT2),
1000                                                 IEN | M5  /* dispc2_data18 */ },
1001         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT3),
1002                                                 IEN | M5  /* dispc2_data15 */ },
1003         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT4),
1004                                                 IEN | M5  /* dispc2_data14 */ },
1005         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT5),
1006                                                 IEN | M5  /* dispc2_data13 */ },
1007         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT6),
1008                                                 IEN | M5  /* dispc2_data12 */ },
1009         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT7),
1010                                                 IEN | M5  /* dispc2_data11 */ },
1011         { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_DATA),
1012                               PTD | OFF_EN | OFF_OUT_PTU | M3  /* gpio_169 */ },
1013         { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_STROBE),
1014                               PTD | OFF_EN | OFF_OUT_PTU | M3  /* gpio_170 */ },
1015         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX0), PTD | IEN | M3  /* gpio_171 */ },
1016         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY0),
1017                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col1 */ },
1018         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX1),
1019                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col2 */ },
1020         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY1),
1021                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col3 */ },
1022         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX2), PTU | IEN | M3  /* gpio_0 */ },
1023         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY2), PTU | IEN | M3  /* gpio_1 */ },
1024         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX0),
1025                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row0 */ },
1026         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY0),
1027                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row1 */ },
1028         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX1),
1029                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row2 */ },
1030         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY1),
1031                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row3 */ },
1032         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX2),
1033                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row4 */ },
1034         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY2),
1035                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row5 */ },
1036         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_CE),
1037                  PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* usba0_otg_ce */ },
1038         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DP),
1039                       IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usba0_otg_dp */ },
1040         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DM),
1041                       IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usba0_otg_dm */ },
1042         { OMAP44XX_CTRL_BASE + CP(FREF_CLK1_OUT), M0  /* fref_clk1_out */ },
1043         { OMAP44XX_CTRL_BASE + CP(FREF_CLK2_OUT),
1044                                                PTD | IEN | M3  /* gpio_182 */ },
1045         { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ1), PTU | IEN | M0  /* sys_nirq1 */ },
1046         { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ2), PTU | IEN | M0  /* sys_nirq2 */ },
1047         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT0), PTU | IEN | M3  /* gpio_184 */ },
1048         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT1), M3  /* gpio_185 */ },
1049         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT2), PTD | IEN | M3  /* gpio_186 */ },
1050         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT3), M3  /* gpio_187 */ },
1051         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT4), M3  /* gpio_188 */ },
1052         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT5), PTD | IEN | M3  /* gpio_189 */ },
1053         { OMAP44XX_CTRL_BASE + CP(DPM_EMU0), IEN | M0  /* dpm_emu0 */ },
1054         { OMAP44XX_CTRL_BASE + CP(DPM_EMU1), IEN | M0  /* dpm_emu1 */ },
1055         { OMAP44XX_CTRL_BASE + CP(DPM_EMU2), IEN | M0  /* dpm_emu2 */ },
1056         { OMAP44XX_CTRL_BASE + CP(DPM_EMU3), IEN | M5  /* dispc2_data10 */ },
1057         { OMAP44XX_CTRL_BASE + CP(DPM_EMU4), IEN | M5  /* dispc2_data9 */ },
1058         { OMAP44XX_CTRL_BASE + CP(DPM_EMU5), IEN | M5  /* dispc2_data16 */ },
1059         { OMAP44XX_CTRL_BASE + CP(DPM_EMU6), IEN | M5  /* dispc2_data17 */ },
1060         { OMAP44XX_CTRL_BASE + CP(DPM_EMU7), IEN | M5  /* dispc2_hsync */ },
1061         { OMAP44XX_CTRL_BASE + CP(DPM_EMU8), IEN | M5  /* dispc2_pclk */ },
1062         { OMAP44XX_CTRL_BASE + CP(DPM_EMU9), IEN | M5  /* dispc2_vsync */ },
1063         { OMAP44XX_CTRL_BASE + CP(DPM_EMU10), IEN | M5  /* dispc2_de */ },
1064         { OMAP44XX_CTRL_BASE + CP(DPM_EMU11), IEN | M5  /* dispc2_data8 */ },
1065         { OMAP44XX_CTRL_BASE + CP(DPM_EMU12), IEN | M5  /* dispc2_data7 */ },
1066         { OMAP44XX_CTRL_BASE + CP(DPM_EMU13), IEN | M5  /* dispc2_data6 */ },
1067         { OMAP44XX_CTRL_BASE + CP(DPM_EMU14), IEN | M5  /* dispc2_data5 */ },
1068         { OMAP44XX_CTRL_BASE + CP(DPM_EMU15), IEN | M5  /* dispc2_data4 */ },
1069         { OMAP44XX_CTRL_BASE + CP(DPM_EMU16), M3  /* gpio_27 */ },
1070         { OMAP44XX_CTRL_BASE + CP(DPM_EMU17), IEN | M5  /* dispc2_data2 */ },
1071         { OMAP44XX_CTRL_BASE + CP(DPM_EMU18), IEN | M5  /* dispc2_data1 */ },
1072         { OMAP44XX_CTRL_BASE + CP(DPM_EMU19), IEN | M5  /* dispc2_data0 */ },
1073         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_IO), IEN | M0  /* sim_io */ },
1074         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CLK), M0  /* sim_clk */ },
1075         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_RESET), M0  /* sim_reset */ },
1076         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CD),
1077                                                  PTU | IEN | M0  /* sim_cd */ },
1078         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_PWRCTRL),
1079                                                         M0  /* sim_pwrctrl */ },
1080         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SR_SCL),
1081                                                  PTU | IEN | M0  /* sr_scl */ },
1082         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SR_SDA),
1083                                                  PTU | IEN | M0  /* sr_sda */ },
1084         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_XTAL_IN), M0  /* # */ },
1085         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_SLICER_IN),
1086                                                      M0  /* fref_slicer_in */ },
1087         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK_IOREQ),
1088                                                      M0  /* fref_clk_ioreq */ },
1089         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK0_OUT),
1090                                                     M2  /* sys_drm_msecure */ },
1091         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1092                                                       PTU | IEN | M0  /* # */ },
1093         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK3_OUT),
1094                                                       M0  /* fref_clk3_out */ },
1095         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ),
1096                                                       PTU | IEN | M0  /* # */ },
1097         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M0  /* # */ },
1098         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_32K), IEN | M0  /* sys_32k */ },
1099         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_NRESPWRON),
1100                                                       M0  /* sys_nrespwron */ },
1101         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_NRESWARM),
1102                                                        M0  /* sys_nreswarm */ },
1103         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_PWR_REQ),
1104                                                   PTU | M0  /* sys_pwr_req */ },
1105         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_PWRON_RESET),
1106                                                           M3  /* gpio_wk29 */ },
1107         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_BOOT6),
1108                                                      IEN | M3  /* gpio_wk9 */ },
1109         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_BOOT7),
1110                                                     IEN | M3  /* gpio_wk10 */ },
1111         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1112                                                            M3 /* gpio_wk30 */ },
1113         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ), M3 /* gpio_wk7 */ },
1114         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M3 /* gpio_wk8 */ },
1115 };
1116
1117 /**********************************************************
1118  * Routine: set_muxconf_regs
1119  * Description: Setting up the configuration Mux registers
1120  *              specific to the hardware. Many pins need
1121  *              to be moved from protect to primary mode.
1122  *********************************************************/
1123 void set_muxconf_regs(void)
1124 {
1125         int n;
1126
1127         for (n = 0; n < sizeof omap4panda_mux / sizeof omap4panda_mux[0]; n++)
1128                 __raw_writew(omap4panda_mux[n].value, omap4panda_mux[n].ads);
1129 }
1130
1131 /******************************************************************************
1132  * Routine: update_mux()
1133  * Description:Update balls which are different between boards.  All should be
1134  *             updated to match functionality.  However, I'm only updating ones
1135  *             which I'll be using for now.  When power comes into play they
1136  *             all need updating.
1137  *****************************************************************************/
1138 void update_mux(u32 btype, u32 mtype)
1139 {
1140         /* REVISIT  */
1141 }
1142
1143 /* optionally do something like blinking LED */
1144 void board_hang(void)
1145 {
1146         while (1)
1147                 ;
1148 }
1149
1150 int nand_init(void)
1151 {
1152         return 0;
1153 }