3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _OMAP34XX_MEM_H_
26 #define _OMAP34XX_MEM_H_
28 #define SDRC_CS0_OSET 0x0
29 #define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
41 /* Memory that can be connected to GPMC */
45 #define GPMC_ONENAND 3
49 #define GPMC_ONENAND_TRY 7
53 /* set the 343x-SDRC incoming address convention */
54 #if defined(SDRC_B_R_C)
55 #define B_ALL (0 << 6) /* bank-row-column */
56 #elif defined(SDRC_B1_R_B0_C)
57 #define B_ALL (1 << 6) /* bank1-row-bank0-column */
58 #elif defined(SDRC_R_B_C)
59 #define B_ALL (2 << 6) /* row-bank-column */
62 /* Future memory combinations based on past */
63 #define SDP_SDRC_MDCFG_MONO_DDR 0x0
64 #define SDP_COMBO_MDCFG_0_DDR 0x0
65 #define SDP_SDRC_MDCFG_0_SDR 0x0
67 /* Slower full frequency range default timings for x32 operation*/
68 #define SDP_SDRC_SHARING 0x00000100
69 #define SDP_SDRC_MR_0_SDR 0x00000031
71 #ifdef CONFIG_3430ZEBU
72 #define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */
74 #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL)
75 #define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
76 #define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL)
77 #define SDP_SDRC_MDCFG_0_DDR_HYNIX (0x03588019|B_ALL)
81 #define MK65KX001AM_SDRC_MCDCFG (0x02584019|B_ALL)
82 #define MK65KX002AM_SDRC_MCDCFG (0x03588019|B_ALL)
84 #define SDP_SDRC_MR_0_DDR 0x00000032
86 /* Diabling power down mode using CKE pin */
87 #define SDP_SDRC_POWER_POP 0x00000081
89 /* optimized timings good for current shipping parts */
90 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
91 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
92 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
93 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
96 #define DLL_WRITEDDRCLKX2DIS 1
99 #define DLL_DLLPHASE_72 0
100 #define DLL_DLLPHASE_90 1
102 // rkw - need to find of 90/72 degree recommendation for speed like before.
103 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
104 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
106 /* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns
107 * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
110 * TRCD = 22.5/7.5 = 3
113 * TRC = 65/7.5 = 8.6->9
119 #define INFINEON_TDAL_133 5
120 #define INFINEON_TDPL_133 2
121 #define INFINEON_TRRD_133 2
122 #define INFINEON_TRCD_133 3
123 #define INFINEON_TRP_133 3
124 #define INFINEON_TRAS_133 6
125 #define INFINEON_TRC_133 9
126 #define INFINEON_TRFC_133 10
127 #define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \
128 |(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \
129 | (INFINEON_TDAL_133))
131 #define INFINEON_TWTR_133 1
132 #define INFINEON_TCKE_133 2
133 #define INFINEON_TXP_133 2
134 #define INFINEON_XSR_133 16
135 #define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \
136 (INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16)
138 #define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133
139 #define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133
142 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns
144 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
145 * TDPL (Twr) = 15/6 = 2.5 -> 3
156 #define INFINEON_TDAL_165 6
157 #define INFINEON_TDPL_165 3
158 #define INFINEON_TRRD_165 2
159 #define INFINEON_TRCD_165 3
160 #define INFINEON_TRP_165 3
161 #define INFINEON_TRAS_165 7
162 #define INFINEON_TRC_165 10
163 #define INFINEON_TRFC_165 12
164 #define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \
165 | (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \
166 (INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165))
168 #define INFINEON_TWTR_165 1
169 #define INFINEON_TCKE_165 2
170 #define INFINEON_TXP_165 2
171 #define INFINEON_XSR_165 20
172 #define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \
173 (INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16)
175 /* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns
176 * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
179 * TRCD = 22.5/7.5 = 3
183 * TRFC = 125/7.5 = 16.6->17
187 * TXSR = 138/7.5 = 18.3->19
188 * TXP = 25/7.5 = 3.3->4
190 #define MICRON_TDAL_133 5
191 #define MICRON_TDPL_133 2
192 #define MICRON_TRRD_133 2
193 #define MICRON_TRCD_133 3
194 #define MICRON_TRP_133 3
195 #define MICRON_TRAS_133 6
196 #define MICRON_TRC_133 10
197 #define MICRON_TRFC_133 17
198 #define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \
199 |(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \
202 #define MICRON_TWTR_133 1
203 #define MICRON_TCKE_133 1
204 #define MICRON_TXSR_133 19
205 #define MICRON_TXP_133 4
206 #define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \
207 | (MICRON_TXSR_133 << 0))
209 #define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133
210 #define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133
212 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns
214 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
215 * TDPL (Twr) = 15/6 = 2.5 -> 3
226 * TXP = 25/6 = 4.1 ~5
228 #define MICRON_TDAL_165 6
229 #define MICRON_TDPL_165 3
230 #define MICRON_TRRD_165 2
231 #define MICRON_TRCD_165 3
232 #define MICRON_TRP_165 3
233 #define MICRON_TRAS_165 7
234 #define MICRON_TRC_165 10
235 #define MICRON_TRFC_165 21
236 #define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \
237 | (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \
238 (MICRON_TDPL_165 << 6) | (MICRON_TDAL_165))
240 #define MICRON_TWTR_165 1
241 #define MICRON_TCKE_165 1
242 #define MICRON_TXP_165 5
243 #define MICRON_XSR_165 23
244 #define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \
245 (MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16)
247 /* Micron part (200MHz optimized) 5 ns
249 #define MICRON_TDAL_200 6
250 #define MICRON_TDPL_200 3
251 #define MICRON_TRRD_200 2
252 #define MICRON_TRCD_200 3
253 #define MICRON_TRP_200 3
254 #define MICRON_TRAS_200 8
255 #define MICRON_TRC_200 11
256 #define MICRON_TRFC_200 15
257 #define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \
258 | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \
259 (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
261 #define MICRON_TWTR_200 2
262 #define MICRON_TCKE_200 4
263 #define MICRON_TXP_200 2
264 #define MICRON_XSR_200 23
265 #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
266 (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
268 /* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
270 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
271 * TDPL (Twr) = 15/6 = 2.5 -> 3
273 * TRCD = 22.5/6 = 3.75 -> 4
277 * TRFC = 140/6 = 23.3 -> 24
281 * TXSR = 200/6 = 33.3 -> 34
282 * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿?
284 #define NUMONYX_TDAL_165 6
285 #define NUMONYX_TDPL_165 3
286 #define NUMONYX_TRRD_165 2
287 #define NUMONYX_TRCD_165 4
288 #define NUMONYX_TRP_165 3
289 #define NUMONYX_TRAS_165 7
290 #define NUMONYX_TRC_165 10
291 #define NUMONYX_TRFC_165 24
292 #define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
293 | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
294 (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
296 #define NUMONYX_TWTR_165 2
297 #define NUMONYX_TCKE_165 2
298 #define NUMONYX_TXP_165 3
299 #define NUMONYX_XSR_165 34
300 #define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
301 (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
304 * Hynix part of Overo (165MHz optimized) 6.06ns
307 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
308 * TDPL (Twr) = 15/6 = 2.5 -> 3
321 #define HYNIX_TDAL_165 6
322 #define HYNIX_TDPL_165 3
323 #define HYNIX_TRRD_165 2
324 #define HYNIX_TRCD_165 3
325 #define HYNIX_TRP_165 3
326 #define HYNIX_TRAS_165 7
327 #define HYNIX_TRC_165 10
328 #define HYNIX_TRFC_165 21
329 #define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \
330 (HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \
331 (HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \
332 (HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \
335 #define HYNIX_TWTR_165 1
336 #define HYNIX_TCKE_165 1
337 #define HYNIX_TXP_165 2
338 #define HYNIX_XSR_165 24
339 #define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \
340 (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \
341 (HYNIX_TWTR_165 << 16))
343 /* Sniper part (165MHz optimized)
345 #define SNIPER_V_ACTIMA_165 0x7A9DB4C6
346 #define SNIPER_V_ACTIMB_165 0x00011218
348 /* Sniper part (200MHz optimized)
350 #define SNIPER_V_ACTIMA_200 0x92E1C4C6
351 #define SNIPER_V_ACTIMB_200 0x0002121C
353 /* New and compatability speed defines */
354 #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
355 # define L3_100MHZ /* Use with <= 100MHz SDRAM */
356 #elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A)
357 # define L3_133MHZ /* Use with <= 133MHz SDRAM*/
358 #elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
359 # define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */
360 #elif defined(PRCM_CLK_CFG2_400MHZ)
361 # define L3_200MHZ /* Use with <= 200MHz SDRAM (L3=200 on 3630) */
365 #if defined(L3_100MHZ)
366 # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_100
367 # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_100
368 #elif defined(L3_133MHZ)
369 # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_133
370 # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_133
371 #elif defined(L3_165MHZ)
372 # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165
373 # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165
374 # define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165
375 # define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165
379 #if defined(L3_100MHZ)
380 # define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_100
381 # define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_100
382 #elif defined(L3_133MHZ)
383 # define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_133
384 # define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_133
385 #elif defined(L3_165MHZ)
386 # define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_165
387 # define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_165
390 #if defined(L3_165MHZ)
391 # define SNIPER_SDRC_ACTIM_CTRLA_0 SNIPER_V_ACTIMA_165
392 # define SNIPER_SDRC_ACTIM_CTRLB_0 SNIPER_V_ACTIMB_165
393 #elif defined(L3_200MHZ)
394 # define SNIPER_SDRC_ACTIM_CTRLA_0 SNIPER_V_ACTIMA_200
395 # define SNIPER_SDRC_ACTIM_CTRLB_0 SNIPER_V_ACTIMB_200
398 #if defined(L3_100MHZ)
399 # define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz
400 #elif defined(L3_133MHZ)
401 # define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz
402 #elif defined(L3_165MHZ)
403 # define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
404 #elif defined(L3_200MHZ)
405 # define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_200MHz
410 * Definitions is as per the following format
411 * # define <PART>_GPMC_CONFIG<x> <value>
413 * PART is the part name e.g. STNOR - Intel Strata Flash
414 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
415 * Value is corresponding value
417 * For every valid PRCM configuration there should be only one definition of
418 * the same. if values are independent of the board, this definition will be
419 * present in this file if values are dependent on the board, then this should
420 * go into corresponding mem-boardName.h file
422 * Currently valid part Names are (PART):
423 * STNOR - Intel Strata Flash
424 * SMNAND - Samsung NAND
425 * M_NAND - Micron Large page x16 NAND
426 * MPDB - H4 MPDB board
428 * ONNAND - Samsung One NAND
430 * include/configs/file.h contains the defn - for all CS we are interested
431 * #define OMAP34XX_GPMC_CSx PART
432 * #define OMAP34XX_GPMC_CSx_SIZE Size
433 * #define OMAP34XX_GPMC_CSx_MAP Map
436 * PART - Part Name as defined above
437 * SIZE - how big is the mapping to be
438 * GPMC_SIZE_128M - 0x8
439 * GPMC_SIZE_64M - 0xC
440 * GPMC_SIZE_32M - 0xE
441 * GPMC_SIZE_16M - 0xF
442 * MAP - Map this CS to which address(GPMC address space)- Absolute address
443 * >>24 before being used.
445 #define GPMC_SIZE_128M 0x8
446 #define GPMC_SIZE_64M 0xC
447 #define GPMC_SIZE_32M 0xE
448 #define GPMC_SIZE_16M 0xF
450 #if defined(L3_100MHZ)
451 # define SMNAND_GPMC_CONFIG1 0x0
452 # define SMNAND_GPMC_CONFIG2 0x00141400
453 # define SMNAND_GPMC_CONFIG3 0x00141400
454 # define SMNAND_GPMC_CONFIG4 0x0F010F01
455 # define SMNAND_GPMC_CONFIG5 0x010C1414
456 # define SMNAND_GPMC_CONFIG6 0x00000A80
458 # define M_NAND_GPMC_CONFIG1 0x00001800
459 # define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2
460 # define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3
461 # define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4
462 # define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5
463 # define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6
464 # define STNOR_GPMC_CONFIG1 0x3
465 # define STNOR_GPMC_CONFIG2 0x000f0f01
466 # define STNOR_GPMC_CONFIG3 0x00050502
467 # define STNOR_GPMC_CONFIG4 0x0C060C06
468 # define STNOR_GPMC_CONFIG5 0x01131F1F
469 # define STNOR_GPMC_CONFIG6 0x0 /* 0? */
470 # define MPDB_GPMC_CONFIG1 0x00011000
471 # define MPDB_GPMC_CONFIG2 0x001F1F00
472 # define MPDB_GPMC_CONFIG3 0x00080802
473 # define MPDB_GPMC_CONFIG4 0x1C091C09
474 # define MPDB_GPMC_CONFIG5 0x031A1F1F
475 # define MPDB_GPMC_CONFIG6 0x000003C2
478 #if defined(L3_133MHZ)
479 # define SMNAND_GPMC_CONFIG1 0x00000800
480 # define SMNAND_GPMC_CONFIG2 0x00141400
481 # define SMNAND_GPMC_CONFIG3 0x00141400
482 # define SMNAND_GPMC_CONFIG4 0x0F010F01
483 # define SMNAND_GPMC_CONFIG5 0x010C1414
484 # define SMNAND_GPMC_CONFIG6 0x00000A80
485 # define SMNAND_GPMC_CONFIG7 0x00000C44
487 # define M_NAND_GPMC_CONFIG1 0x00001800
488 # define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2
489 # define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3
490 # define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4
491 # define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5
492 # define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6
493 # define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7
495 # define STNOR_GPMC_CONFIG1 0x1203
496 # define STNOR_GPMC_CONFIG2 0x00151501
497 # define STNOR_GPMC_CONFIG3 0x00060602
498 # define STNOR_GPMC_CONFIG4 0x10081008
499 # define STNOR_GPMC_CONFIG5 0x01131F1F
500 # define STNOR_GPMC_CONFIG6 0x000004c4
502 # define SIBNOR_GPMC_CONFIG1 0x1200
503 # define SIBNOR_GPMC_CONFIG2 0x001f1f00
504 # define SIBNOR_GPMC_CONFIG3 0x00080802
505 # define SIBNOR_GPMC_CONFIG4 0x1C091C09
506 # define SIBNOR_GPMC_CONFIG5 0x01131F1F
507 # define SIBNOR_GPMC_CONFIG6 0x000003C2
509 # define MPDB_GPMC_CONFIG1 0x00011000
510 # define MPDB_GPMC_CONFIG2 0x001f1f01
511 # define MPDB_GPMC_CONFIG3 0x00080803
512 # define MPDB_GPMC_CONFIG4 0x1C091C09
513 # define MPDB_GPMC_CONFIG5 0x041f1F1F
514 # define MPDB_GPMC_CONFIG6 0x000004C4
516 # define P2_GPMC_CONFIG1 0x0
517 # define P2_GPMC_CONFIG2 0x0
518 # define P2_GPMC_CONFIG3 0x0
519 # define P2_GPMC_CONFIG4 0x0
520 # define P2_GPMC_CONFIG5 0x0
521 # define P2_GPMC_CONFIG6 0x0
523 # define ONENAND_GPMC_CONFIG1 0x00001200
524 # define ONENAND_GPMC_CONFIG2 0x000c0c01
525 # define ONENAND_GPMC_CONFIG3 0x00030301
526 # define ONENAND_GPMC_CONFIG4 0x0c040c04
527 # define ONENAND_GPMC_CONFIG5 0x010C1010
528 # define ONENAND_GPMC_CONFIG6 0x00000000
530 #endif /* endif L3_133MHZ */
532 #if defined (L3_165MHZ)
533 # define SMNAND_GPMC_CONFIG1 0x00000800
534 # define SMNAND_GPMC_CONFIG2 0x00141400
535 # define SMNAND_GPMC_CONFIG3 0x00141400
536 # define SMNAND_GPMC_CONFIG4 0x0F010F01
537 # define SMNAND_GPMC_CONFIG5 0x010C1414
538 # define SMNAND_GPMC_CONFIG6 0x1F0F0A80
539 # define SMNAND_GPMC_CONFIG7 0x00000C44
541 # define M_NAND_GPMC_CONFIG1 0x00001800
542 # define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2
543 # define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3
544 # define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4
545 # define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5
546 # define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6
547 # define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7
549 # define STNOR_GPMC_CONFIG1 0x3
550 # define STNOR_GPMC_CONFIG2 0x00151501
551 # define STNOR_GPMC_CONFIG3 0x00060602
552 # define STNOR_GPMC_CONFIG4 0x11091109
553 # define STNOR_GPMC_CONFIG5 0x01141F1F
554 # define STNOR_GPMC_CONFIG6 0x000004c4
556 # define SIBNOR_GPMC_CONFIG1 0x1200
557 # define SIBNOR_GPMC_CONFIG2 0x001f1f00
558 # define SIBNOR_GPMC_CONFIG3 0x00080802
559 # define SIBNOR_GPMC_CONFIG4 0x1C091C09
560 # define SIBNOR_GPMC_CONFIG5 0x01131F1F
561 # define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
563 # define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
564 # define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
565 # define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
566 # define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
567 # define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
568 # define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
570 # define MPDB_GPMC_CONFIG1 0x00011000
571 # define MPDB_GPMC_CONFIG2 0x001f1f01
572 # define MPDB_GPMC_CONFIG3 0x00080803
573 # define MPDB_GPMC_CONFIG4 0x1c0b1c0a
574 # define MPDB_GPMC_CONFIG5 0x041f1F1F
575 # define MPDB_GPMC_CONFIG6 0x1F0F04C4
577 # define P2_GPMC_CONFIG1 0x0
578 # define P2_GPMC_CONFIG2 0x0
579 # define P2_GPMC_CONFIG3 0x0
580 # define P2_GPMC_CONFIG4 0x0
581 # define P2_GPMC_CONFIG5 0x0
582 # define P2_GPMC_CONFIG6 0x0
584 # define ONENAND_GPMC_CONFIG1 0x00001200
585 # define ONENAND_GPMC_CONFIG2 0x000F0F01
586 # define ONENAND_GPMC_CONFIG3 0x00030301
587 # define ONENAND_GPMC_CONFIG4 0x0F040F04
588 # define ONENAND_GPMC_CONFIG5 0x010F1010
589 # define ONENAND_GPMC_CONFIG6 0x1F060000
593 #if defined(L3_200MHZ)
594 # define SMNAND_GPMC_CONFIG1 0x00000800
595 # define SMNAND_GPMC_CONFIG2 0x00060600
596 # define SMNAND_GPMC_CONFIG3 0x00060401
597 # define SMNAND_GPMC_CONFIG4 0x05010801
598 # define SMNAND_GPMC_CONFIG5 0x00090B0B
599 # define SMNAND_GPMC_CONFIG6 0x050001C0
600 # define SMNAND_GPMC_CONFIG7 0x00000C44
602 # define M_NAND_GPMC_CONFIG1 0x00001800
603 # define M_NAND_GPMC_CONFIG2 0x00181800
604 # define M_NAND_GPMC_CONFIG3 0x00181800
605 # define M_NAND_GPMC_CONFIG4 0x12021202
606 # define M_NAND_GPMC_CONFIG5 0x020f1818
607 # define M_NAND_GPMC_CONFIG6 0x00000c80
608 # define M_NAND_GPMC_CONFIG7 0x00000870
610 # define STNOR_GPMC_CONFIG1 0x3
611 # define STNOR_GPMC_CONFIG2 0x00151501
612 # define STNOR_GPMC_CONFIG3 0x00060602
613 # define STNOR_GPMC_CONFIG4 0x11091109
614 # define STNOR_GPMC_CONFIG5 0x01141F1F
615 # define STNOR_GPMC_CONFIG6 0x1F0F04c4
617 # define SIBNOR_GPMC_CONFIG1 0x1210
618 # define SIBNOR_GPMC_CONFIG2 0x00131300
619 # define SIBNOR_GPMC_CONFIG3 0x00050501
620 # define SIBNOR_GPMC_CONFIG4 0x11061106
621 # define SIBNOR_GPMC_CONFIG5 0x010c1313
622 # define SIBNOR_GPMC_CONFIG6 0x130902c2
624 # define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
625 # define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
626 # define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
627 # define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
628 # define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
629 # define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
631 # define MPDB_GPMC_CONFIG1 0x00011000
632 # define MPDB_GPMC_CONFIG2 0x001f1f01
633 # define MPDB_GPMC_CONFIG3 0x00080803
634 # define MPDB_GPMC_CONFIG4 0x1c0b1c0a
635 # define MPDB_GPMC_CONFIG5 0x041f1F1F
636 # define MPDB_GPMC_CONFIG6 0x1F0F04C4
638 # define LAB_ENET_GPMC_CONFIG1 0x00611000
639 # define LAB_ENET_GPMC_CONFIG2 0x001F1F01
640 # define LAB_ENET_GPMC_CONFIG3 0x00080803
641 # define LAB_ENET_GPMC_CONFIG4 0x1D091D09
642 # define LAB_ENET_GPMC_CONFIG5 0x041D1F1F
643 # define LAB_ENET_GPMC_CONFIG6 0x1D0904C4
645 # define P2_GPMC_CONFIG1 0x0
646 # define P2_GPMC_CONFIG2 0x0
647 # define P2_GPMC_CONFIG3 0x0
648 # define P2_GPMC_CONFIG4 0x0
649 # define P2_GPMC_CONFIG5 0x0
650 # define P2_GPMC_CONFIG6 0x0
652 # define ONENAND_GPMC_CONFIG1 0x00001200
653 # define ONENAND_GPMC_CONFIG2 0x000F0F01
654 # define ONENAND_GPMC_CONFIG3 0x00030301
655 # define ONENAND_GPMC_CONFIG4 0x0F040F04
656 # define ONENAND_GPMC_CONFIG5 0x010F1010
657 # define ONENAND_GPMC_CONFIG6 0x1F060000
659 #endif /* L3_200MHZ */
661 /* max number of GPMC Chip Selects */
662 #define GPMC_MAX_CS 8
663 /* max number of GPMC regs */
664 #define GPMC_MAX_REG 7
667 #define PISMO1_NAND 2
670 #define PISMO1_ONENAND 5
671 #define POP_ONENAND 5
673 #define PISMO2_NAND_CS0 7
674 #define PISMO2_NAND_CS1 8
676 /* make it readable for the gpmc_init */
677 #define PISMO1_NOR_BASE FLASH_BASE
678 #define PISMO1_NAND_BASE NAND_BASE
679 #define PISMO2_CS0_BASE PISMO2_MAP1
680 #define PISMO1_ONEN_BASE ONENAND_MAP
681 #define POP_ONEN_BASE ONENAND_MAP
682 #define DBG_MPDB_BASE DEBUG_BASE
684 #endif /* endif _OMAP34XX_MEM_H_ */