LG Optimus Black (P970) support

[x-loader-sniper.git] / include / asm / arch-omap3 / mem.h

diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
index 154114a..1941692 100644 (file)
--- a/include/asm/arch-omap3/mem.h
+++ b/include/asm/arch-omap3/mem.h
@@ -340,6 +340,16 @@ typedef enum {
                (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \
                (HYNIX_TWTR_165 << 16))
 
+/* Sniper part (165MHz optimized)
+  */
+#define SNIPER_V_ACTIMA_165 0x7A9DB4C6
+#define SNIPER_V_ACTIMB_165 0x00011218
+
+/* Sniper part (200MHz optimized)
+  */
+#define SNIPER_V_ACTIMA_200 0x92E1C4C6
+#define SNIPER_V_ACTIMB_200 0x0002121C
+
 /* New and compatability speed defines */
 #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
 # define L3_100MHZ   /* Use with <= 100MHz SDRAM */
@@ -347,6 +357,9 @@ typedef enum {
 # define L3_133MHZ    /* Use with <= 133MHz SDRAM*/
 #elif  defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
 # define L3_165MHZ    /* Use with <= 165MHz SDRAM (L3=166 on 3430) */
+#elif defined(PRCM_CLK_CFG2_400MHZ)
+# define L3_200MHZ    /* Use with <= 200MHz SDRAM (L3=200 on 3630) */
+#else
 #endif
 
 #if defined(L3_100MHZ)
@@ -374,12 +387,22 @@ typedef enum {
 # define INFINEON_SDRC_ACTIM_CTRLB_0     INFINEON_V_ACTIMB_165
 #endif
 
+#if defined(L3_165MHZ)
+# define SNIPER_SDRC_ACTIM_CTRLA_0     SNIPER_V_ACTIMA_165
+# define SNIPER_SDRC_ACTIM_CTRLB_0     SNIPER_V_ACTIMB_165
+#elif defined(L3_200MHZ)
+# define SNIPER_SDRC_ACTIM_CTRLA_0     SNIPER_V_ACTIMA_200
+# define SNIPER_SDRC_ACTIM_CTRLB_0     SNIPER_V_ACTIMB_200
+#endif
+
 #if defined(L3_100MHZ)
 # define SDP_SDRC_RFR_CTRL          SDP_3430_SDRC_RFR_CTRL_100MHz
 #elif defined(L3_133MHZ)
 # define SDP_SDRC_RFR_CTRL          SDP_3430_SDRC_RFR_CTRL_133MHz
 #elif  defined(L3_165MHZ)
 # define SDP_SDRC_RFR_CTRL          SDP_3430_SDRC_RFR_CTRL_165MHz
+#elif  defined(L3_200MHZ)
+# define SDP_SDRC_RFR_CTRL          SDP_3430_SDRC_RFR_CTRL_200MHz
 #endif
 
 /*
@@ -567,6 +590,74 @@ typedef enum {
 
 #endif
 
+#if defined(L3_200MHZ)
+# define SMNAND_GPMC_CONFIG1 0x00000800
+# define SMNAND_GPMC_CONFIG2 0x00060600
+# define SMNAND_GPMC_CONFIG3 0x00060401
+# define SMNAND_GPMC_CONFIG4 0x05010801
+# define SMNAND_GPMC_CONFIG5 0x00090B0B
+# define SMNAND_GPMC_CONFIG6 0x050001C0
+# define SMNAND_GPMC_CONFIG7 0x00000C44
+
+# define M_NAND_GPMC_CONFIG1 0x00001800
+# define M_NAND_GPMC_CONFIG2 0x00181800
+# define M_NAND_GPMC_CONFIG3 0x00181800
+# define M_NAND_GPMC_CONFIG4 0x12021202
+# define M_NAND_GPMC_CONFIG5 0x020f1818
+# define M_NAND_GPMC_CONFIG6 0x00000c80
+# define M_NAND_GPMC_CONFIG7 0x00000870
+
+# define STNOR_GPMC_CONFIG1  0x3
+# define STNOR_GPMC_CONFIG2  0x00151501
+# define STNOR_GPMC_CONFIG3  0x00060602
+# define STNOR_GPMC_CONFIG4  0x11091109
+# define STNOR_GPMC_CONFIG5  0x01141F1F
+# define STNOR_GPMC_CONFIG6  0x1F0F04c4
+
+# define SIBNOR_GPMC_CONFIG1  0x1210
+# define SIBNOR_GPMC_CONFIG2  0x00131300
+# define SIBNOR_GPMC_CONFIG3  0x00050501
+# define SIBNOR_GPMC_CONFIG4  0x11061106
+# define SIBNOR_GPMC_CONFIG5  0x010c1313
+# define SIBNOR_GPMC_CONFIG6  0x130902c2
+
+# define SDPV2_MPDB_GPMC_CONFIG1  0x00611200
+# define SDPV2_MPDB_GPMC_CONFIG2  0x001F1F01
+# define SDPV2_MPDB_GPMC_CONFIG3  0x00080803
+# define SDPV2_MPDB_GPMC_CONFIG4  0x1D091D09
+# define SDPV2_MPDB_GPMC_CONFIG5  0x041D1F1F
+# define SDPV2_MPDB_GPMC_CONFIG6  0x1D0904C4
+
+# define MPDB_GPMC_CONFIG1  0x00011000
+# define MPDB_GPMC_CONFIG2  0x001f1f01
+# define MPDB_GPMC_CONFIG3  0x00080803
+# define MPDB_GPMC_CONFIG4  0x1c0b1c0a
+# define MPDB_GPMC_CONFIG5  0x041f1F1F
+# define MPDB_GPMC_CONFIG6  0x1F0F04C4
+
+# define LAB_ENET_GPMC_CONFIG1  0x00611000
+# define LAB_ENET_GPMC_CONFIG2  0x001F1F01
+# define LAB_ENET_GPMC_CONFIG3  0x00080803
+# define LAB_ENET_GPMC_CONFIG4  0x1D091D09
+# define LAB_ENET_GPMC_CONFIG5  0x041D1F1F
+# define LAB_ENET_GPMC_CONFIG6  0x1D0904C4
+
+# define P2_GPMC_CONFIG1  0x0
+# define P2_GPMC_CONFIG2  0x0
+# define P2_GPMC_CONFIG3  0x0
+# define P2_GPMC_CONFIG4  0x0
+# define P2_GPMC_CONFIG5  0x0
+# define P2_GPMC_CONFIG6  0x0
+
+# define ONENAND_GPMC_CONFIG1 0x00001200
+# define ONENAND_GPMC_CONFIG2 0x000F0F01
+# define ONENAND_GPMC_CONFIG3 0x00030301
+# define ONENAND_GPMC_CONFIG4 0x0F040F04
+# define ONENAND_GPMC_CONFIG5 0x010F1010
+# define ONENAND_GPMC_CONFIG6 0x1F060000
+
+#endif /* L3_200MHZ */
+
 /* max number of GPMC Chip Selects */
 #define GPMC_MAX_CS    8
 /* max number of GPMC regs */