--- /dev/null
+/****************************************************************************\r
+ *\r
+ * Copyright(c) 2010 Yamaha Corporation. All rights reserved.\r
+ *\r
+ * Module : mcdriver.h\r
+ *\r
+ * Description : MC Driver header\r
+ *\r
+ * Version : 1.0.0 2010.07.05\r
+ *\r
+ ****************************************************************************/\r
+\r
+#ifndef _MCDRIVER_H_\r
+#define _MCDRIVER_H_\r
+\r
+#include "mctypedef.h"\r
+\r
+\r
+\r
+signed long McDrv_Ctrl( UINT32 dCmd, void* pvPrm, UINT32 dPrm );\r
+\r
+\r
+\r
+\r
+/* return value */\r
+#define MCDRV_SUCCESS ((SINT32)0)\r
+#define MCDRV_ERROR_ARGUMENT (-1)\r
+#define MCDRV_ERROR_TIMEOUT (-2)\r
+#define MCDRV_ERROR_INIT (-3)\r
+#define MCDRV_ERROR_RESOURCEOVER (-4)\r
+#define MCDRV_ERROR_STATE (-5)\r
+\r
+#define MCDRV_ERROR (-10)\r
+\r
+\r
+/* dCmd */\r
+#define MCDRV_INIT (0)\r
+#define MCDRV_TERM (1)\r
+#define MCDRV_READ_REG (2)\r
+#define MCDRV_WRITE_REG (3)\r
+#define MCDRV_GET_PATH (4)\r
+#define MCDRV_SET_PATH (5)\r
+#define MCDRV_GET_VOLUME (6)\r
+#define MCDRV_SET_VOLUME (7)\r
+#define MCDRV_GET_DIGITALIO (8)\r
+#define MCDRV_SET_DIGITALIO (9)\r
+#define MCDRV_GET_DAC (10)\r
+#define MCDRV_SET_DAC (11)\r
+#define MCDRV_GET_ADC (12)\r
+#define MCDRV_SET_ADC (13)\r
+#define MCDRV_GET_SP (14)\r
+#define MCDRV_SET_SP (15)\r
+#define MCDRV_GET_DNG (16)\r
+#define MCDRV_SET_DNG (17)\r
+#define MCDRV_SET_AUDIOENGINE (18)\r
+#define MCDRV_SET_AUDIOENGINE_EX (19)\r
+#define MCDRV_SET_CDSP (20)\r
+#define MCDRV_GET_CDSP_PARAM (21)\r
+#define MCDRV_SET_CDSP_PARAM (22)\r
+#define MCDRV_REGISTER_CDSP_CB (23)\r
+#define MCDRV_GET_PDM (24)\r
+#define MCDRV_SET_PDM (25)\r
+#define MCDRV_SET_DTMF (26)\r
+#define MCDRV_CONFIG_GP (27)\r
+#define MCDRV_MASK_GP (28)\r
+#define MCDRV_GETSET_GP (29)\r
+#define MCDRV_GET_PEAK (30)\r
+#define MCDRV_IRQ (31)\r
+#define MCDRV_UPDATE_CLOCK (32)\r
+#define MCDRV_SWITCH_CLOCK (33)\r
+#define MCDRV_GET_SYSEQ (34)\r
+#define MCDRV_SET_SYSEQ (35)\r
+\r
+/* pvPrm */\r
+/* init */\r
+/* MCDRV_INIT_INFO bCkSel setting */\r
+#define MCDRV_CKSEL_CMOS (0x00)\r
+#define MCDRV_CKSEL_TCXO (0xC0)\r
+#define MCDRV_CKSEL_CMOS_TCXO (0x80)\r
+#define MCDRV_CKSEL_TCXO_CMOS (0x40)\r
+\r
+/* MCDRV_INIT_INFO bXXXHiz setting */\r
+#define MCDRV_DAHIZ_LOW (0)\r
+#define MCDRV_DAHIZ_HIZ (1)\r
+\r
+/* CDRV_INIT_INFO bPcmHiz setting */\r
+#define MCDRV_PCMHIZ_LOW (0)\r
+#define MCDRV_PCMHIZ_HIZ (1)\r
+\r
+/* MCDRV_INIT_INFO bSvolStep setting */\r
+#define MCDRV_SVOLSTEP_0137 (0)\r
+#define MCDRV_SVOLSTEP_0274 (1)\r
+#define MCDRV_SVOLSTEP_0548 (2)\r
+#define MCDRV_SVOLSTEP_1096 (3)\r
+\r
+/* MCDRV_INIT_INFO bLinexxDif setting */\r
+#define MCDRV_LINE_STEREO (0)\r
+#define MCDRV_LINE_DIF (1)\r
+\r
+/* MCDRV_INIT_INFO bSpmn setting */\r
+#define MCDRV_SPMN_ON (0)\r
+#define MCDRV_SPMN_OFF (1)\r
+\r
+/* MCDRV_INIT_INFO bMicxSng setting */\r
+#define MCDRV_MIC_DIF (0)\r
+#define MCDRV_MIC_SINGLE (1)\r
+\r
+/* MCDRV_INIT_INFO bPowerMode setting */\r
+#define MCDRV_POWMODE_NORMAL (0)\r
+#define MCDRV_POWMODE_CLKON (1)\r
+#define MCDRV_POWMODE_VREFON (2)\r
+#define MCDRV_POWMODE_CLKVREFON (3)\r
+#define MCDRV_POWMODE_FULL (4)\r
+\r
+/* bSpHiz setting */\r
+#define MCDRV_SPHIZ_PULLDOWN (0)\r
+#define MCDRV_SPHIZ_HIZ (1)\r
+\r
+/* MCDRV_INIT_INFO bLdo setting */\r
+#define MCDRV_LDO_OFF (0)\r
+#define MCDRV_LDO_ON (1)\r
+\r
+/* MCDRV_INIT_INFO bPadxFunc setting */\r
+#define MCDRV_PAD_GPIO (0)\r
+#define MCDRV_PAD_PDMCK (1)\r
+#define MCDRV_PAD_PDMDI (2)\r
+#define MCDRV_PAD_IRQ (3)\r
+\r
+/* MCDRV_INIT_INFO bAvddLev/bVrefLev setting */\r
+#define MCDRV_OUTLEV_0 (0)\r
+#define MCDRV_OUTLEV_1 (1)\r
+#define MCDRV_OUTLEV_2 (2)\r
+#define MCDRV_OUTLEV_3 (3)\r
+#define MCDRV_OUTLEV_4 (4)\r
+#define MCDRV_OUTLEV_5 (5)\r
+#define MCDRV_OUTLEV_6 (6)\r
+#define MCDRV_OUTLEV_7 (7)\r
+\r
+/* MCDRV_INIT_INFO bDclGain setting */\r
+#define MCDRV_DCLGAIN_0 (0)\r
+#define MCDRV_DCLGAIN_6 (1)\r
+#define MCDRV_DCLGAIN_12 (2)\r
+#define MCDRV_DCLGAIN_18 (3)\r
+\r
+/* MCDRV_INIT_INFO bDclLimit setting */\r
+#define MCDRV_DCLLIMIT_0 (0)\r
+#define MCDRV_DCLLIMIT_116 (1)\r
+#define MCDRV_DCLLIMIT_250 (2)\r
+#define MCDRV_DCLLIMIT_602 (3)\r
+\r
+/* MCDRV_INIT_INFO bCpMod setting */\r
+#define MCDRV_CPMOD_ON (0)\r
+#define MCDRV_CPMOD_OFF (1)\r
+\r
+typedef struct\r
+{\r
+ UINT32 dAdHpf;\r
+ UINT32 dMic1Cin;\r
+ UINT32 dMic2Cin;\r
+ UINT32 dMic3Cin;\r
+ UINT32 dLine1Cin;\r
+ UINT32 dLine2Cin;\r
+ UINT32 dVrefRdy1;\r
+ UINT32 dVrefRdy2;\r
+ UINT32 dHpRdy;\r
+ UINT32 dSpRdy;\r
+ UINT32 dPdm;\r
+ UINT32 dAnaRdyInterval;\r
+ UINT32 dSvolInterval;\r
+ UINT32 dAnaRdyTimeOut;\r
+ UINT32 dSvolTimeOut;\r
+} MCDRV_WAIT_TIME;\r
+\r
+typedef struct\r
+{\r
+ UINT8 bCkSel;\r
+ UINT8 bDivR0;\r
+ UINT8 bDivF0;\r
+ UINT8 bDivR1;\r
+ UINT8 bDivF1;\r
+ UINT8 bRange0;\r
+ UINT8 bRange1;\r
+ UINT8 bBypass;\r
+ UINT8 bDioSdo0Hiz;\r
+ UINT8 bDioSdo1Hiz;\r
+ UINT8 bDioSdo2Hiz;\r
+ UINT8 bDioClk0Hiz;\r
+ UINT8 bDioClk1Hiz;\r
+ UINT8 bDioClk2Hiz;\r
+ UINT8 bPcmHiz;\r
+ UINT8 bLineIn1Dif;\r
+ UINT8 bLineIn2Dif;\r
+ UINT8 bLineOut1Dif;\r
+ UINT8 bLineOut2Dif;\r
+ UINT8 bSpmn;\r
+ UINT8 bMic1Sng;\r
+ UINT8 bMic2Sng;\r
+ UINT8 bMic3Sng;\r
+ UINT8 bPowerMode;\r
+ UINT8 bSpHiz;\r
+ UINT8 bLdo;\r
+ UINT8 bPad0Func;\r
+ UINT8 bPad1Func;\r
+ UINT8 bPad2Func;\r
+ UINT8 bAvddLev;\r
+ UINT8 bVrefLev;\r
+ UINT8 bDclGain;\r
+ UINT8 bDclLimit;\r
+ UINT8 bCpMod;\r
+ UINT8 bReserved1;\r
+ UINT8 bReserved2;\r
+ UINT8 bReserved3;\r
+ UINT8 bReserved4;\r
+ UINT8 bReserved5;\r
+ MCDRV_WAIT_TIME sWaitTime;\r
+} MCDRV_INIT_INFO;\r
+\r
+/* update clock */\r
+typedef struct\r
+{\r
+ UINT8 bCkSel;\r
+ UINT8 bDivR0;\r
+ UINT8 bDivF0;\r
+ UINT8 bDivR1;\r
+ UINT8 bDivF1;\r
+ UINT8 bRange0;\r
+ UINT8 bRange1;\r
+ UINT8 bBypass;\r
+} MCDRV_CLOCK_INFO;\r
+\r
+/* switch clock */\r
+/* MCDRV_CLKSW_INFO bClkSrc setting */\r
+#define MCDRV_CLKSW_CLKI0 (0x00)\r
+#define MCDRV_CLKSW_CLKI1 (0x01)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bClkSrc;\r
+} MCDRV_CLKSW_INFO;\r
+\r
+/* set/get path */\r
+#define SOURCE_BLOCK_NUM (7)\r
+#define MCDRV_SRC_MIC1_BLOCK (0)\r
+#define MCDRV_SRC_MIC2_BLOCK (0)\r
+#define MCDRV_SRC_MIC3_BLOCK (0)\r
+#define MCDRV_SRC_LINE1_L_BLOCK (1)\r
+#define MCDRV_SRC_LINE1_R_BLOCK (1)\r
+#define MCDRV_SRC_LINE1_M_BLOCK (1)\r
+#define MCDRV_SRC_LINE2_L_BLOCK (2)\r
+#define MCDRV_SRC_LINE2_R_BLOCK (2)\r
+#define MCDRV_SRC_LINE2_M_BLOCK (2)\r
+#define MCDRV_SRC_DIR0_BLOCK (3)\r
+#define MCDRV_SRC_DIR1_BLOCK (3)\r
+#define MCDRV_SRC_DIR2_BLOCK (3)\r
+#define MCDRV_SRC_DIR2_DIRECT_BLOCK (3)\r
+#define MCDRV_SRC_DTMF_BLOCK (4)\r
+#define MCDRV_SRC_PDM_BLOCK (4)\r
+#define MCDRV_SRC_ADC0_BLOCK (4)\r
+#define MCDRV_SRC_ADC1_BLOCK (4)\r
+#define MCDRV_SRC_DAC_L_BLOCK (5)\r
+#define MCDRV_SRC_DAC_R_BLOCK (5)\r
+#define MCDRV_SRC_DAC_M_BLOCK (5)\r
+#define MCDRV_SRC_MIX_BLOCK (6)\r
+#define MCDRV_SRC_AE_BLOCK (6)\r
+#define MCDRV_SRC_CDSP_BLOCK (6)\r
+#define MCDRV_SRC_CDSP_DIRECT_BLOCK (6)\r
+\r
+#define MCDRV_SRC0_MIC1_ON (0x01)\r
+#define MCDRV_SRC0_MIC1_OFF (0x02)\r
+#define MCDRV_SRC0_MIC2_ON (0x04)\r
+#define MCDRV_SRC0_MIC2_OFF (0x08)\r
+#define MCDRV_SRC0_MIC3_ON (0x10)\r
+#define MCDRV_SRC0_MIC3_OFF (0x20)\r
+#define MCDRV_SRC1_LINE1_L_ON (0x01)\r
+#define MCDRV_SRC1_LINE1_L_OFF (0x02)\r
+#define MCDRV_SRC1_LINE1_R_ON (0x04)\r
+#define MCDRV_SRC1_LINE1_R_OFF (0x08)\r
+#define MCDRV_SRC1_LINE1_M_ON (0x10)\r
+#define MCDRV_SRC1_LINE1_M_OFF (0x20)\r
+#define MCDRV_SRC2_LINE2_L_ON (0x01)\r
+#define MCDRV_SRC2_LINE2_L_OFF (0x02)\r
+#define MCDRV_SRC2_LINE2_R_ON (0x04)\r
+#define MCDRV_SRC2_LINE2_R_OFF (0x08)\r
+#define MCDRV_SRC2_LINE2_M_ON (0x10)\r
+#define MCDRV_SRC2_LINE2_M_OFF (0x20)\r
+#define MCDRV_SRC3_DIR0_ON (0x01)\r
+#define MCDRV_SRC3_DIR0_OFF (0x02)\r
+#define MCDRV_SRC3_DIR1_ON (0x04)\r
+#define MCDRV_SRC3_DIR1_OFF (0x08)\r
+#define MCDRV_SRC3_DIR2_ON (0x10)\r
+#define MCDRV_SRC3_DIR2_OFF (0x20)\r
+#define MCDRV_SRC3_DIR2_DIRECT_ON (0x40)\r
+#define MCDRV_SRC3_DIR2_DIRECT_OFF (0x80)\r
+#define MCDRV_SRC4_DTMF_ON (0x01)\r
+#define MCDRV_SRC4_DTMF_OFF (0x02)\r
+#define MCDRV_SRC4_PDM_ON (0x04)\r
+#define MCDRV_SRC4_PDM_OFF (0x08)\r
+#define MCDRV_SRC4_ADC0_ON (0x10)\r
+#define MCDRV_SRC4_ADC0_OFF (0x20)\r
+#define MCDRV_SRC4_ADC1_ON (0x40)\r
+#define MCDRV_SRC4_ADC1_OFF (0x80)\r
+#define MCDRV_SRC5_DAC_L_ON (0x01)\r
+#define MCDRV_SRC5_DAC_L_OFF (0x02)\r
+#define MCDRV_SRC5_DAC_R_ON (0x04)\r
+#define MCDRV_SRC5_DAC_R_OFF (0x08)\r
+#define MCDRV_SRC5_DAC_M_ON (0x10)\r
+#define MCDRV_SRC5_DAC_M_OFF (0x20)\r
+#define MCDRV_SRC6_MIX_ON (0x01)\r
+#define MCDRV_SRC6_MIX_OFF (0x02)\r
+#define MCDRV_SRC6_AE_ON (0x04)\r
+#define MCDRV_SRC6_AE_OFF (0x08)\r
+#define MCDRV_SRC6_CDSP_ON (0x10)\r
+#define MCDRV_SRC6_CDSP_OFF (0x20)\r
+#define MCDRV_SRC6_CDSP_DIRECT_ON (0x40)\r
+#define MCDRV_SRC6_CDSP_DIRECT_OFF (0x80)\r
+\r
+typedef struct\r
+{\r
+ UINT8 abSrcOnOff[SOURCE_BLOCK_NUM];\r
+} MCDRV_CHANNEL;\r
+\r
+#define HP_PATH_CHANNELS (2)\r
+#define SP_PATH_CHANNELS (2)\r
+#define RC_PATH_CHANNELS (1)\r
+#define LOUT1_PATH_CHANNELS (2)\r
+#define LOUT2_PATH_CHANNELS (2)\r
+#define PEAK_PATH_CHANNELS (1)\r
+#define DIT0_PATH_CHANNELS (1)\r
+#define DIT1_PATH_CHANNELS (1)\r
+#define DIT2_PATH_CHANNELS (1)\r
+#define DAC_PATH_CHANNELS (2)\r
+#define AE_PATH_CHANNELS (1)\r
+#define CDSP_PATH_CHANNELS (4)\r
+#define ADC0_PATH_CHANNELS (2)\r
+#define ADC1_PATH_CHANNELS (1)\r
+#define MIX_PATH_CHANNELS (1)\r
+#define BIAS_PATH_CHANNELS (1)\r
+\r
+typedef struct\r
+{\r
+ MCDRV_CHANNEL asHpOut[HP_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asSpOut[SP_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asRcOut[RC_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asLout1[LOUT1_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asLout2[LOUT2_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asPeak[PEAK_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asDit0[DIT0_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asDit1[DIT1_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asDit2[DIT2_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asDac[DAC_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asAe[AE_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asCdsp[CDSP_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asAdc0[ADC0_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asAdc1[ADC1_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asMix[MIX_PATH_CHANNELS];\r
+ MCDRV_CHANNEL asBias[BIAS_PATH_CHANNELS];\r
+} MCDRV_PATH_INFO;\r
+\r
+/* set/get vol */\r
+#define MCDRV_VOL_UPDATE (0x0001)\r
+\r
+#define AD0_VOL_CHANNELS (2)\r
+#define AD1_VOL_CHANNELS (1)\r
+#define AENG6_VOL_CHANNELS (2)\r
+#define PDM_VOL_CHANNELS (2)\r
+#define DTMF_VOL_CHANNELS (2)\r
+#define DIO0_VOL_CHANNELS (2)\r
+#define DIO1_VOL_CHANNELS (2)\r
+#define DIO2_VOL_CHANNELS (2)\r
+#define DTFM_VOL_CHANNELS (2)\r
+#define DAC_VOL_CHANNELS (2)\r
+\r
+#define LIN1_VOL_CHANNELS (2)\r
+#define LIN2_VOL_CHANNELS (2)\r
+#define MIC1_VOL_CHANNELS (1)\r
+#define MIC2_VOL_CHANNELS (1)\r
+#define MIC3_VOL_CHANNELS (1)\r
+#define HP_VOL_CHANNELS (2)\r
+#define SP_VOL_CHANNELS (2)\r
+#define RC_VOL_CHANNELS (1)\r
+#define LOUT1_VOL_CHANNELS (2)\r
+#define LOUT2_VOL_CHANNELS (2)\r
+#define HPGAIN_VOL_CHANNELS (1)\r
+\r
+typedef struct\r
+{\r
+ SINT16 aswD_Ad0[AD0_VOL_CHANNELS];\r
+ SINT16 aswD_Ad1[AD1_VOL_CHANNELS];\r
+ SINT16 aswD_Aeng6[AENG6_VOL_CHANNELS];\r
+ SINT16 aswD_Pdm[PDM_VOL_CHANNELS];\r
+ SINT16 aswD_Dtmfb[DTMF_VOL_CHANNELS];\r
+ SINT16 aswD_Dir0[DIO0_VOL_CHANNELS];\r
+ SINT16 aswD_Dir1[DIO1_VOL_CHANNELS];\r
+ SINT16 aswD_Dir2[DIO2_VOL_CHANNELS];\r
+ SINT16 aswD_Ad0Att[AD0_VOL_CHANNELS];\r
+ SINT16 aswD_Ad1Att[AD1_VOL_CHANNELS];\r
+ SINT16 aswD_Dir0Att[DIO0_VOL_CHANNELS];\r
+ SINT16 aswD_Dir1Att[DIO1_VOL_CHANNELS];\r
+ SINT16 aswD_Dir2Att[DIO2_VOL_CHANNELS];\r
+ SINT16 aswD_SideTone[PDM_VOL_CHANNELS];\r
+ SINT16 aswD_DtmfAtt[DTFM_VOL_CHANNELS];\r
+ SINT16 aswD_DacMaster[DAC_VOL_CHANNELS];\r
+ SINT16 aswD_DacVoice[DAC_VOL_CHANNELS];\r
+ SINT16 aswD_DacAtt[DAC_VOL_CHANNELS];\r
+ SINT16 aswD_Dit0[DIO0_VOL_CHANNELS];\r
+ SINT16 aswD_Dit1[DIO1_VOL_CHANNELS];\r
+ SINT16 aswD_Dit2[DIO2_VOL_CHANNELS];\r
+ SINT16 aswA_Ad0[AD0_VOL_CHANNELS];\r
+ SINT16 aswA_Ad1[AD1_VOL_CHANNELS];\r
+ SINT16 aswA_Lin1[LIN1_VOL_CHANNELS];\r
+ SINT16 aswA_Lin2[LIN2_VOL_CHANNELS];\r
+ SINT16 aswA_Mic1[MIC1_VOL_CHANNELS];\r
+ SINT16 aswA_Mic2[MIC2_VOL_CHANNELS];\r
+ SINT16 aswA_Mic3[MIC3_VOL_CHANNELS];\r
+ SINT16 aswA_Hp[HP_VOL_CHANNELS];\r
+ SINT16 aswA_Sp[SP_VOL_CHANNELS];\r
+ SINT16 aswA_Rc[RC_VOL_CHANNELS];\r
+ SINT16 aswA_Lout1[LOUT1_VOL_CHANNELS];\r
+ SINT16 aswA_Lout2[LOUT2_VOL_CHANNELS];\r
+ SINT16 aswA_Mic1Gain[MIC1_VOL_CHANNELS];\r
+ SINT16 aswA_Mic2Gain[MIC2_VOL_CHANNELS];\r
+ SINT16 aswA_Mic3Gain[MIC3_VOL_CHANNELS];\r
+ SINT16 aswA_HpGain[HPGAIN_VOL_CHANNELS];\r
+} MCDRV_VOL_INFO;\r
+\r
+/* set/get digitalio */\r
+#define MCDRV_DIO0_COM_UPDATE_FLAG ((UINT32)0x00000001)\r
+#define MCDRV_DIO0_DIR_UPDATE_FLAG ((UINT32)0x00000002)\r
+#define MCDRV_DIO0_DIT_UPDATE_FLAG ((UINT32)0x00000004)\r
+#define MCDRV_DIO1_COM_UPDATE_FLAG ((UINT32)0x00000008)\r
+#define MCDRV_DIO1_DIR_UPDATE_FLAG ((UINT32)0x00000010)\r
+#define MCDRV_DIO1_DIT_UPDATE_FLAG ((UINT32)0x00000020)\r
+#define MCDRV_DIO2_COM_UPDATE_FLAG ((UINT32)0x00000040)\r
+#define MCDRV_DIO2_DIR_UPDATE_FLAG ((UINT32)0x00000080)\r
+#define MCDRV_DIO2_DIT_UPDATE_FLAG ((UINT32)0x00000100)\r
+\r
+/* MCDRV_DIO_COMMON bMasterSlave setting */\r
+#define MCDRV_DIO_SLAVE (0)\r
+#define MCDRV_DIO_MASTER (1)\r
+\r
+/* MCDRV_DIO_COMMON bDigitalAutoFs setting */\r
+#define MCDRV_AUTOFS_OFF (0)\r
+#define MCDRV_AUTOFS_ON (1)\r
+\r
+/* MCDRV_DIO_COMMON bFs setting */\r
+#define MCDRV_FS_48000 (0)\r
+#define MCDRV_FS_44100 (1)\r
+#define MCDRV_FS_32000 (2)\r
+#define MCDRV_FS_24000 (4)\r
+#define MCDRV_FS_22050 (5)\r
+#define MCDRV_FS_16000 (6)\r
+#define MCDRV_FS_12000 (8)\r
+#define MCDRV_FS_11025 (9)\r
+#define MCDRV_FS_8000 (10)\r
+\r
+/* MCDRV_DIO_COMMON bBckFs setting */\r
+#define MCDRV_BCKFS_64 (0)\r
+#define MCDRV_BCKFS_48 (1)\r
+#define MCDRV_BCKFS_32 (2)\r
+#define MCDRV_BCKFS_512 (4)\r
+#define MCDRV_BCKFS_256 (5)\r
+#define MCDRV_BCKFS_128 (6)\r
+#define MCDRV_BCKFS_16 (7)\r
+\r
+/* MCDRV_DIO_COMMON bInterface setting */\r
+#define MCDRV_DIO_DA (0)\r
+#define MCDRV_DIO_PCM (1)\r
+\r
+/* MCDRV_DIO_COMMON bBckInvert setting */\r
+#define MCDRV_BCLK_NORMAL (0)\r
+#define MCDRV_BCLK_INVERT (1)\r
+\r
+/* MCDRV_DIO_COMMON bPcmHizTim setting */\r
+#define MCDRV_PCMHIZTIM_FALLING (0)\r
+#define MCDRV_PCMHIZTIM_RISING (1)\r
+\r
+/* MCDRV_DIO_COMMON bPcmClkDown setting */\r
+#define MCDRV_PCM_CLKDOWN_OFF (0)\r
+#define MCDRV_PCM_CLKDOWN_HALF (1)\r
+\r
+/* MCDRV_DIO_COMMON bPcmFrame setting */\r
+#define MCDRV_PCM_SHORTFRAME (0)\r
+#define MCDRV_PCM_LONGFRAME (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bMasterSlave;\r
+ UINT8 bAutoFs;\r
+ UINT8 bFs;\r
+ UINT8 bBckFs;\r
+ UINT8 bInterface;\r
+ UINT8 bBckInvert;\r
+ UINT8 bPcmHizTim;\r
+ UINT8 bPcmClkDown;\r
+ UINT8 bPcmFrame;\r
+ UINT8 bPcmHighPeriod;\r
+} MCDRV_DIO_COMMON;\r
+\r
+/* MCDRV_DA_FORMAT bBitSel setting */\r
+#define MCDRV_BITSEL_16 (0)\r
+#define MCDRV_BITSEL_20 (1)\r
+#define MCDRV_BITSEL_24 (2)\r
+\r
+/* MCDRV_DA_FORMAT bMode setting */\r
+#define MCDRV_DAMODE_HEADALIGN (0)\r
+#define MCDRV_DAMODE_I2S (1)\r
+#define MCDRV_DAMODE_TAILALIGN (2)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bBitSel;\r
+ UINT8 bMode;\r
+} MCDRV_DA_FORMAT;\r
+\r
+/* MCDRV_PCM_FORMAT bMono setting */\r
+#define MCDRV_PCM_STEREO (0)\r
+#define MCDRV_PCM_MONO (1)\r
+\r
+/* MCDRV_PCM_FORMAT bOrder setting */\r
+#define MCDRV_PCM_MSB_FIRST (0)\r
+#define MCDRV_PCM_LSB_FIRST (1)\r
+#define MCDRV_PCM_MSB_FIRST_SIGN (2)\r
+#define MCDRV_PCM_LSB_FIRST_SIGN (3)\r
+#define MCDRV_PCM_MSB_FIRST_ZERO (4)\r
+#define MCDRV_PCM_LSB_FIRST_ZERO (5)\r
+\r
+/* MCDRV_PCM_FORMAT bLaw setting */\r
+#define MCDRV_PCM_LINEAR (0)\r
+#define MCDRV_PCM_ALAW (1)\r
+#define MCDRV_PCM_MULAW (2)\r
+\r
+/* MCDRV_PCM_FORMAT bBitSel setting */\r
+#define MCDRV_PCM_BITSEL_8 (0)\r
+#define MCDRV_PCM_BITSEL_13 (1)\r
+#define MCDRV_PCM_BITSEL_14 (2)\r
+#define MCDRV_PCM_BITSEL_16 (3)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bMono;\r
+ UINT8 bOrder;\r
+ UINT8 bLaw;\r
+ UINT8 bBitSel;\r
+} MCDRV_PCM_FORMAT;\r
+\r
+#define DIO_CHANNELS (2)\r
+typedef struct\r
+{\r
+ UINT16 wSrcRate;\r
+ MCDRV_DA_FORMAT sDaFormat;\r
+ MCDRV_PCM_FORMAT sPcmFormat;\r
+ UINT8 abSlot[DIO_CHANNELS];\r
+} MCDRV_DIO_DIR;\r
+\r
+typedef struct\r
+{\r
+ UINT16 wSrcRate;\r
+ MCDRV_DA_FORMAT sDaFormat;\r
+ MCDRV_PCM_FORMAT sPcmFormat;\r
+ UINT8 abSlot[DIO_CHANNELS];\r
+} MCDRV_DIO_DIT;\r
+\r
+typedef struct\r
+{\r
+ MCDRV_DIO_COMMON sDioCommon;\r
+ MCDRV_DIO_DIR sDir;\r
+ MCDRV_DIO_DIT sDit;\r
+} MCDRV_DIO_PORT;\r
+\r
+#define IOPORT_NUM (3)\r
+typedef struct\r
+{\r
+ MCDRV_DIO_PORT asPortInfo[IOPORT_NUM];\r
+} MCDRV_DIO_INFO;\r
+\r
+/* set dac */\r
+#define MCDRV_DAC_MSWP_UPDATE_FLAG ((UINT32)0x01)\r
+#define MCDRV_DAC_VSWP_UPDATE_FLAG ((UINT32)0x02)\r
+#define MCDRV_DAC_HPF_UPDATE_FLAG ((UINT32)0x04)\r
+\r
+/* MCDRV_DAC_INFO bMasterSwap/bVoiceSwap setting */\r
+#define MCDRV_DSWAP_OFF (0)\r
+#define MCDRV_DSWAP_SWAP (1)\r
+#define MCDRV_DSWAP_MUTE (2)\r
+#define MCDRV_DSWAP_RMVCENTER (3)\r
+#define MCDRV_DSWAP_MONO (4)\r
+#define MCDRV_DSWAP_MONOHALF (5)\r
+#define MCDRV_DSWAP_BOTHL (6)\r
+#define MCDRV_DSWAP_BOTHR (7)\r
+\r
+/* MCDRV_DAC_INFO bDcCut setting */\r
+#define MCDRV_DCCUT_ON (0)\r
+#define MCDRV_DCCUT_OFF (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bMasterSwap;\r
+ UINT8 bVoiceSwap;\r
+ UINT8 bDcCut;\r
+} MCDRV_DAC_INFO;\r
+\r
+/* set adc */\r
+#define MCDRV_ADCADJ_UPDATE_FLAG ((UINT32)0x00000001)\r
+#define MCDRV_ADCAGC_UPDATE_FLAG ((UINT32)0x00000002)\r
+#define MCDRV_ADCMONO_UPDATE_FLAG ((UINT32)0x00000004)\r
+\r
+/* MCDRV_ADC_INFO bAgcAdjust setting */\r
+#define MCDRV_AGCADJ_24 (0)\r
+#define MCDRV_AGCADJ_18 (1)\r
+#define MCDRV_AGCADJ_12 (2)\r
+#define MCDRV_AGCADJ_0 (3)\r
+\r
+/* MCDRV_ADC_INFO bAgcOn setting */\r
+#define MCDRV_AGC_OFF (0)\r
+#define MCDRV_AGC_ON (1)\r
+\r
+/* MCDRV_ADC_INFO bMono setting */\r
+#define MCDRV_ADC_STEREO (0)\r
+#define MCDRV_ADC_MONO (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bAgcAdjust;\r
+ UINT8 bAgcOn;\r
+ UINT8 bMono;\r
+} MCDRV_ADC_INFO;\r
+\r
+/* set sp */\r
+/* MCDRV_SP_INFO bSwap setting */\r
+#define MCDRV_SPSWAP_OFF (0)\r
+#define MCDRV_SPSWAP_SWAP (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bSwap;\r
+} MCDRV_SP_INFO;\r
+\r
+/* set dng */\r
+#define DNG_ITEM_NUM (3)\r
+#define MCDRV_DNG_ITEM_HP (0)\r
+#define MCDRV_DNG_ITEM_SP (1)\r
+#define MCDRV_DNG_ITEM_RC (2)\r
+\r
+#define MCDRV_DNGSW_HP_UPDATE_FLAG ((UINT32)0x00000001)\r
+#define MCDRV_DNGTHRES_HP_UPDATE_FLAG ((UINT32)0x00000002)\r
+#define MCDRV_DNGHOLD_HP_UPDATE_FLAG ((UINT32)0x00000004)\r
+#define MCDRV_DNGATK_HP_UPDATE_FLAG ((UINT32)0x00000008)\r
+#define MCDRV_DNGREL_HP_UPDATE_FLAG ((UINT32)0x00000010)\r
+#define MCDRV_DNGTARGET_HP_UPDATE_FLAG ((UINT32)0x00000020)\r
+#define MCDRV_DNGSW_SP_UPDATE_FLAG ((UINT32)0x00000100)\r
+#define MCDRV_DNGTHRES_SP_UPDATE_FLAG ((UINT32)0x00000200)\r
+#define MCDRV_DNGHOLD_SP_UPDATE_FLAG ((UINT32)0x00000400)\r
+#define MCDRV_DNGATK_SP_UPDATE_FLAG ((UINT32)0x00000800)\r
+#define MCDRV_DNGREL_SP_UPDATE_FLAG ((UINT32)0x00001000)\r
+#define MCDRV_DNGTARGET_SP_UPDATE_FLAG ((UINT32)0x00002000)\r
+#define MCDRV_DNGSW_RC_UPDATE_FLAG ((UINT32)0x00010000)\r
+#define MCDRV_DNGTHRES_RC_UPDATE_FLAG ((UINT32)0x00020000)\r
+#define MCDRV_DNGHOLD_RC_UPDATE_FLAG ((UINT32)0x00040000)\r
+#define MCDRV_DNGATK_RC_UPDATE_FLAG ((UINT32)0x00080000)\r
+#define MCDRV_DNGREL_RC_UPDATE_FLAG ((UINT32)0x00100000)\r
+#define MCDRV_DNGTARGET_RC_UPDATE_FLAG ((UINT32)0x00200000)\r
+\r
+/* MCDRV_DNG_INFO bOnOff setting */\r
+#define MCDRV_DNG_OFF (0)\r
+#define MCDRV_DNG_ON (1)\r
+\r
+/* MCDRV_DNG_INFO bThreshold setting */\r
+#define MCDRV_DNG_THRES_30 (0)\r
+#define MCDRV_DNG_THRES_36 (1)\r
+#define MCDRV_DNG_THRES_42 (2)\r
+#define MCDRV_DNG_THRES_48 (3)\r
+#define MCDRV_DNG_THRES_54 (4)\r
+#define MCDRV_DNG_THRES_60 (5)\r
+#define MCDRV_DNG_THRES_66 (6)\r
+#define MCDRV_DNG_THRES_72 (7)\r
+#define MCDRV_DNG_THRES_78 (8)\r
+#define MCDRV_DNG_THRES_84 (9)\r
+\r
+/* MCDRV_DNG_INFO bHold setting */\r
+#define MCDRV_DNG_HOLD_30 (0)\r
+#define MCDRV_DNG_HOLD_120 (1)\r
+#define MCDRV_DNG_HOLD_500 (2)\r
+\r
+/* MCDRV_DNG_INFO bAttack setting */\r
+#define MCDRV_DNG_ATTACK_25 (0)\r
+#define MCDRV_DNG_ATTACK_100 (1)\r
+#define MCDRV_DNG_ATTACK_400 (2)\r
+#define MCDRV_DNG_ATTACK_800 (3)\r
+\r
+/* MCDRV_DNG_INFO bRelease setting */\r
+#define MCDRV_DNG_RELEASE_7950 (0)\r
+#define MCDRV_DNG_RELEASE_470 (1)\r
+#define MCDRV_DNG_RELEASE_940 (2)\r
+\r
+/* MCDRV_DNG_INFO bTarget setting */\r
+#define MCDRV_DNG_TARGET_6 (0)\r
+#define MCDRV_DNG_TARGET_9 (1)\r
+#define MCDRV_DNG_TARGET_12 (2)\r
+#define MCDRV_DNG_TARGET_15 (3)\r
+#define MCDRV_DNG_TARGET_18 (4)\r
+#define MCDRV_DNG_TARGET_MUTE (5)\r
+\r
+typedef struct\r
+{\r
+ UINT8 abOnOff[DNG_ITEM_NUM];\r
+ UINT8 abThreshold[DNG_ITEM_NUM];\r
+ UINT8 abHold[DNG_ITEM_NUM];\r
+ UINT8 abAttack[DNG_ITEM_NUM];\r
+ UINT8 abRelease[DNG_ITEM_NUM];\r
+ UINT8 abTarget[DNG_ITEM_NUM];\r
+} MCDRV_DNG_INFO;\r
+\r
+/* set audio engine */\r
+#define MCDRV_AEUPDATE_FLAG_BEXWIDE_ONOFF ((UINT32)0x00000001)\r
+#define MCDRV_AEUPDATE_FLAG_DRC_ONOFF ((UINT32)0x00000002)\r
+#define MCDRV_AEUPDATE_FLAG_EQ5_ONOFF ((UINT32)0x00000004)\r
+#define MCDRV_AEUPDATE_FLAG_EQ3_ONOFF ((UINT32)0x00000008)\r
+#define MCDRV_AEUPDATE_FLAG_BEX ((UINT32)0x00000010)\r
+#define MCDRV_AEUPDATE_FLAG_WIDE ((UINT32)0x00000020)\r
+#define MCDRV_AEUPDATE_FLAG_DRC ((UINT32)0x00000040)\r
+#define MCDRV_AEUPDATE_FLAG_EQ5 ((UINT32)0x00000080)\r
+#define MCDRV_AEUPDATE_FLAG_EQ3 ((UINT32)0x00000100)\r
+\r
+/* MCDRV_AE_INFO bOnOff setting */\r
+#define MCDRV_BEXWIDE_ON (0x01)\r
+#define MCDRV_DRC_ON (0x02)\r
+#define MCDRV_EQ5_ON (0x04)\r
+#define MCDRV_EQ3_ON (0x08)\r
+\r
+#define BEX_PARAM_SIZE (104)\r
+#define WIDE_PARAM_SIZE (20)\r
+#define DRC_PARAM_SIZE (256)\r
+#define EQ5_PARAM_SIZE (105)\r
+#define EQ3_PARAM_SIZE (75)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bOnOff;\r
+ UINT8 abBex[BEX_PARAM_SIZE];\r
+ UINT8 abWide[WIDE_PARAM_SIZE];\r
+ UINT8 abDrc[DRC_PARAM_SIZE];\r
+ UINT8 abEq5[EQ5_PARAM_SIZE];\r
+ UINT8 abEq3[EQ3_PARAM_SIZE];\r
+} MCDRV_AE_INFO;\r
+\r
+/* set cdsp param */\r
+typedef struct\r
+{\r
+ UINT8 bId;\r
+ UINT8 abParam[16];\r
+} MCDRV_CDSPPARAM;\r
+\r
+/* register cdsp cb */\r
+/* dEvtType */\r
+#define MCDRV_CDSP_EVT_ERROR (0)\r
+#define MCDRV_CDSP_EVT_PARAM (1)\r
+\r
+/* dEvtPrm */\r
+#define MCDRV_CDSP_PRG_ERROR (0)\r
+#define MCDRV_CDSP_PRG_ERROR_FATAL (1)\r
+#define MCDRV_CDSP_SYS_ERROR (2)\r
+\r
+/* set pdm */\r
+#define MCDRV_PDMCLK_UPDATE_FLAG ((UINT32)0x00000001)\r
+#define MCDRV_PDMADJ_UPDATE_FLAG ((UINT32)0x00000002)\r
+#define MCDRV_PDMAGC_UPDATE_FLAG ((UINT32)0x00000004)\r
+#define MCDRV_PDMEDGE_UPDATE_FLAG ((UINT32)0x00000008)\r
+#define MCDRV_PDMWAIT_UPDATE_FLAG ((UINT32)0x00000010)\r
+#define MCDRV_PDMSEL_UPDATE_FLAG ((UINT32)0x00000020)\r
+#define MCDRV_PDMMONO_UPDATE_FLAG ((UINT32)0x00000040)\r
+\r
+/* MCDRV_PDM_INFO bClk setting */\r
+#define MCDRV_PDM_CLK_128 (1)\r
+#define MCDRV_PDM_CLK_64 (2)\r
+#define MCDRV_PDM_CLK_32 (3)\r
+\r
+/* MCDRV_PDM_INFO bPdmEdge setting */\r
+#define MCDRV_PDMEDGE_LH (0)\r
+#define MCDRV_PDMEDGE_HL (1)\r
+\r
+/* MCDRV_PDM_INFO bPdmWait setting */\r
+#define MCDRV_PDMWAIT_0 (0)\r
+#define MCDRV_PDMWAIT_1 (1)\r
+#define MCDRV_PDMWAIT_10 (2)\r
+#define MCDRV_PDMWAIT_20 (3)\r
+\r
+/* MCDRV_PDM_INFO bPdmSel setting */\r
+#define MCDRV_PDMSEL_L1R2 (0)\r
+#define MCDRV_PDMSEL_L2R1 (1)\r
+#define MCDRV_PDMSEL_L1R1 (2)\r
+#define MCDRV_PDMSEL_L2R2 (3)\r
+\r
+/* MCDRV_PDM_INFO bMono setting */\r
+#define MCDRV_PDM_STEREO (0)\r
+#define MCDRV_PDM_MONO (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bClk;\r
+ UINT8 bAgcAdjust;\r
+ UINT8 bAgcOn;\r
+ UINT8 bPdmEdge;\r
+ UINT8 bPdmWait;\r
+ UINT8 bPdmSel;\r
+ UINT8 bMono;\r
+} MCDRV_PDM_INFO;\r
+\r
+/* set dtmf */\r
+typedef struct\r
+{\r
+ UINT8 bSinGen0Vol;\r
+ UINT8 bSinGen1Vol;\r
+ UINT16 wSinGen0Freq;\r
+ UINT16 wSinGen1Freq;\r
+ UINT8 bSinGenGate;\r
+ UINT8 bSinGenMode;\r
+ UINT8 bSinGenLoop;\r
+} MCDRV_DTMF_PARAM;\r
+\r
+/* MCDRV_DTMF_INFO bOnOff setting */\r
+#define MCDRV_DTMF_ON (0)\r
+#define MCDRV_DTMF_OFF (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bOnOff;\r
+ MCDRV_DTMF_PARAM sParam;\r
+} MCDRV_DTMF_INFO;\r
+\r
+/* config gp */\r
+#define GPIO_PAD_NUM (2)\r
+\r
+/* MCDRV_GP_MODE abGpDdr setting */\r
+#define MCDRV_GPDDR_IN (0)\r
+#define MCDRV_GPDDR_OUT (1)\r
+\r
+/* MCDRV_GP_MODE abGpMode setting */\r
+#define MCDRV_GPMODE_RISING (0)\r
+#define MCDRV_GPMODE_FALLING (1)\r
+#define MCDRV_GPMODE_BOTH (2)\r
+\r
+/* MCDRV_GP_MODE abGpHost setting */\r
+#define MCDRV_GPHOST_SCU (0)\r
+#define MCDRV_GPHOST_CDSP (1)\r
+\r
+/* MCDRV_GP_MODE abGpInvert setting */\r
+#define MCDRV_GPINV_NORMAL (0)\r
+#define MCDRV_GPINV_INVERT (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 abGpDdr[GPIO_PAD_NUM];\r
+ UINT8 abGpMode[GPIO_PAD_NUM];\r
+ UINT8 abGpHost[GPIO_PAD_NUM];\r
+ UINT8 abGpInvert[GPIO_PAD_NUM];\r
+} MCDRV_GP_MODE;\r
+\r
+/* mask gp */\r
+#define MCDRV_GPMASK_OFF (0)\r
+#define MCDRV_GPMASK_ON (1)\r
+\r
+#define MCDRV_GP_PAD0 ((UINT32)0)\r
+#define MCDRV_GP_PAD1 ((UINT32)1)\r
+\r
+/* getset gp */\r
+#define MCDRV_GP_LOW (0)\r
+#define MCDRV_GP_HIGH (1)\r
+\r
+/* get peak */\r
+#define PEAK_CHANNELS (2)\r
+typedef struct\r
+{\r
+ SINT16 aswPeak[PEAK_CHANNELS];\r
+} MCDRV_PEAK;\r
+\r
+/* set/get syseq */\r
+#define MCDRV_SYSEQ_ONOFF_UPDATE_FLAG ((UINT32)0x00000001)\r
+#define MCDRV_SYSEQ_PARAM_UPDATE_FLAG ((UINT32)0x00000002)\r
+\r
+/* MCDRV_SYSEQ_INFO bOnOff setting */\r
+#define MCDRV_SYSEQ_OFF (0)\r
+#define MCDRV_SYSEQ_ON (1)\r
+\r
+typedef struct\r
+{\r
+ UINT8 bOnOff;\r
+ UINT8 abParam[15];\r
+} MCDRV_SYSEQ_INFO;\r
+\r
+/* read_reg, write_reg */\r
+#define MCDRV_REGTYPE_A (0)\r
+#define MCDRV_REGTYPE_B_BASE (1)\r
+#define MCDRV_REGTYPE_B_MIXER (2)\r
+#define MCDRV_REGTYPE_B_AE (3)\r
+#define MCDRV_REGTYPE_B_CDSP (4)\r
+#define MCDRV_REGTYPE_B_CODEC (5)\r
+#define MCDRV_REGTYPE_B_ANALOG (6)\r
+typedef struct\r
+{\r
+ UINT8 bRegType;\r
+ UINT8 bAddress;\r
+ UINT8 bData;\r
+} MCDRV_REG_INFO;\r
+\r
+\r
+#endif /* _MCDRIVER_H_ */\r